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@@ -175,39 +175,6 @@ relocate_code:
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callr r8
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ret
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-/*
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- * dly_clks -- Nios2 (like Nios1) doesn't have a timebase in
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- * the core. For simple delay loops, we do our best by counting
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- * instruction cycles.
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- *
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- * Instruction performance varies based on the core. For cores
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- * with icache and static/dynamic branch prediction (II/f, II/s):
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- *
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- * Normal ALU (e.g. add, cmp, etc): 1 cycle
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- * Branch (correctly predicted, taken): 2 cycles
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- * Negative offset is predicted (II/s).
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- *
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- * For cores without icache and no branch prediction (II/e):
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- *
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- * Normal ALU (e.g. add, cmp, etc): 6 cycles
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- * Branch (no prediction): 6 cycles
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- *
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- * For simplicity, if an instruction cache is implemented we
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- * assume II/f or II/s. Otherwise, we use the II/e.
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- *
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- */
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- .globl dly_clks
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-
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-dly_clks:
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-
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-#if (CONFIG_SYS_ICACHE_SIZE > 0)
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- subi r4, r4, 3 /* 3 clocks/loop */
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-#else
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- subi r4, r4, 12 /* 12 clocks/loop */
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-#endif
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- bge r4, r0, dly_clks
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- ret
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-
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.data
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.globl version_string
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