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@@ -17,7 +17,6 @@
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(17)
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-#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
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static const struct bcr_regs sdc_regs[] = {
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{
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@@ -36,11 +35,17 @@ static const struct bcr_regs sdc_regs[] = {
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}
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};
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-static struct gpll0_ctrl gpll0_ctrl = {
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+static struct pll_vote_clk gpll0_vote_clk = {
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.status = GPLL0_STATUS,
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.status_bit = GPLL0_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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- .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
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+ .vote_bit = BIT(0),
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+};
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+
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+static struct vote_clk gcc_blsp1_ahb_clk = {
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+ .cbcr_reg = BLSP1_AHB_CBCR,
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+ .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
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+ .vote_bit = BIT(10),
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};
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/* SDHCI */
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@@ -55,7 +60,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
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/* 800Mhz/div, gpll0 */
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clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
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CFG_CLK_SRC_GPLL0);
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- clk_enable_gpll0(priv->base, &gpll0_ctrl);
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+ clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
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return rate;
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@@ -72,12 +77,16 @@ static const struct bcr_regs uart2_regs = {
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/* UART: 115200 */
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static int clk_init_uart(struct msm_clk_priv *priv)
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{
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- /* Enable iface clk */
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- clk_enable_cbc(priv->base + BLSP1_AHB_CBCR);
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+ /* Enable AHB clock */
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+ clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
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+
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/* 7372800 uart block clock @ GPLL0 */
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clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
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CFG_CLK_SRC_GPLL0);
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- clk_enable_gpll0(priv->base, &gpll0_ctrl);
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+
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+ /* Vote for gpll0 clock */
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+ clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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+
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/* Enable core clk */
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clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
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