Merge git://git.denx.de/u-boot-imx

arch/arm/Kconfig

@@ -497,13 +497,6 @@ config TARGET_X600
 	select SUPPORT_SPL
 	select PL011_SERIAL
 
-config TARGET_MX31PDK
-	bool "Support mx31pdk"
-	select BOARD_LATE_INIT
-	select CPU_ARM1136
-	select SUPPORT_SPL
-	select BOARD_EARLY_INIT_F
-
 config TARGET_WOODBURN
 	bool "Support woodburn"
 	select CPU_ARM1136
@@ -665,6 +658,10 @@ config ARCH_MX28
 	select PL011_SERIAL
 	select SUPPORT_SPL
 
+config ARCH_MX31
+	bool "NXP i.MX31 family"
+	select CPU_ARM1136
+
 config ARCH_MX7ULP
         bool "NXP MX7ULP"
 	select CPU_V7A
@@ -1305,6 +1302,8 @@ source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
 source "arch/arm/mach-imx/mx2/Kconfig"
 
+source "arch/arm/mach-imx/mx3/Kconfig"
+
 source "arch/arm/mach-imx/mx5/Kconfig"
 
 source "arch/arm/mach-imx/mx6/Kconfig"
@@ -1392,7 +1391,6 @@ source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
-source "board/freescale/mx31pdk/Kconfig"
 source "board/freescale/mx35pdk/Kconfig"
 source "board/freescale/s32v234evb/Kconfig"
 source "board/gdsys/a38x/Kconfig"

arch/arm/dts/Makefile

@@ -400,24 +400,33 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
 
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
-	imx6sl-evk.dtb \
-	imx6sll-evk.dtb \
+dtb-$(CONFIG_MX6QDL) += \
 	imx6dl-icore.dtb \
 	imx6dl-icore-mipi.dtb \
 	imx6dl-icore-rqs.dtb \
+	imx6dl-mamoj.dtb \
 	imx6q-cm-fx6.dtb \
 	imx6q-icore.dtb \
 	imx6q-icore-mipi.dtb \
 	imx6q-icore-rqs.dtb \
-	imx6q-logicpd.dtb \
+	imx6q-logicpd.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
+
+dtb-$(CONFIG_MX6SL) += imx6sll-evk.dtb
+
+dtb-$(CONFIG_MX6SX) += \
 	imx6sx-sabreauto.dtb \
-	imx6sx-sdb.dtb \
+	imx6sx-sdb.dtb
+
+dtb-$(CONFIG_MX6UL) += \
 	imx6ul-geam-kit.dtb \
 	imx6ul-isiot-emmc.dtb \
 	imx6ul-isiot-nand.dtb \
 	imx6ul-opos6uldev.dtb
 
+dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
+
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 	imx7d-sdb.dtb
 

arch/arm/dts/imx53-kp.dts

@@ -0,0 +1,135 @@
+/*
+ * Copyright 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:     GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "imx53.dtsi"
+#include "imx53-pinfunc.h"
+
+/ {
+	model = "K+P iMX53";
+	compatible = "kp,imx53-kp", "fsl,imx53";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eth>;
+	phy-mode = "rmii";
+	phy-reset-gpios = <&gpio7 6 0>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	clock_frequency = <100000>;
+
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+
+	pmic: mc34708@8 {
+		compatible = "fsl,mc34708";
+		reg = <0x8>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	clock_frequency = <100000>;
+
+	scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx53-kp {
+		pinctrl_eth: ethgrp {
+			fsl,pins = <
+				MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
+				MX53_PAD_FEC_MDC__FEC_MDC 0x4
+				MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
+				MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
+				MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
+				MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
+				MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
+				MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
+				/* The RX_ER pin needs to be pull down */
+				/* for this device */
+				MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1c0
+				MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
+				>;
+		};
+
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				/* PHY RESET */
+				MX53_PAD_PATA_DA_0__GPIO7_6 0x182
+				/* VBUS_PWR_EN */
+				MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
+				/* BOOSTER_OFF */
+				MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX53_PAD_KEY_ROW3__I2C2_SDA
+						 (0x1ee | IMX_PAD_SION)
+				MX53_PAD_KEY_COL3__I2C2_SCL
+						 (0x1ee | IMX_PAD_SION)
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grpgpio {
+			fsl,pins = <
+				MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4
+				MX53_PAD_KEY_COL3__GPIO4_12 0x1e4
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX53_PAD_GPIO_6__I2C3_SDA (0x1ee | IMX_PAD_SION)
+				MX53_PAD_GPIO_5__I2C3_SCL (0x1ee | IMX_PAD_SION)
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grpgpio {
+			fsl,pins = <
+				MX53_PAD_GPIO_6__GPIO1_6 0x1e4
+				MX53_PAD_GPIO_5__GPIO1_5 0x1e4
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
+				MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
+			>;
+		};
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};

arch/arm/dts/imx53-pinfunc.h

@@ -10,6 +10,7 @@
 #ifndef __DTS_IMX53_PINFUNC_H
 #define __DTS_IMX53_PINFUNC_H
 
+#define IMX_PAD_SION       0x40000000
 /*
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>

arch/arm/dts/imx53.dtsi

@@ -21,6 +21,16 @@
 / {
 	aliases {
 		serial1 = &uart2;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		gpio6 = &gpio7;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
 	};
 
 	tzic: tz-interrupt-controller@fffc000 {
@@ -73,6 +83,66 @@
 				#clock-cells = <1>;
 			};
 
+			gpio1: gpio@53f84000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f84000 0x4000>;
+				interrupts = <50 51>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio@53f88000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f88000 0x4000>;
+				interrupts = <52 53>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio@53f8c000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f8c000 0x4000>;
+				interrupts = <54 55>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio@53f90000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53f90000 0x4000>;
+				interrupts = <56 57>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio@53fdc000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53fdc000 0x4000>;
+				interrupts = <103 104>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio6: gpio@53fe0000 {
+				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
+				reg = <0x53fe0000 0x4000>;
+				interrupts = <105 106>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
 			gpio7: gpio@53fe4000 {
 				compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 				reg = <0x53fe4000 0x4000>;
@@ -82,6 +152,16 @@
 				interrupt-controller;
 				#interrupt-cells = <2>;
 			};
+
+			i2c3: i2c@53fec000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x53fec000 0x4000>;
+				interrupts = <64>;
+				clocks = <&clks IMX5_CLK_I2C3_GATE>;
+				status = "disabled";
+			};
 		};
 
 		aips@60000000 {	/* AIPS2 */
@@ -102,7 +182,6 @@
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 			};
 
-
 			fec: ethernet@63fec000 {
 				compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 				reg = <0x63fec000 0x4000>;
@@ -113,6 +192,26 @@
 				clock-names = "ipg", "ahb", "ptp";
 				status = "disabled";
 			};
+
+			i2c2: i2c@63fc4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc4000 0x4000>;
+				interrupts = <63>;
+				clocks = <&clks IMX5_CLK_I2C2_GATE>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@63fc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
+				reg = <0x63fc8000 0x4000>;
+				interrupts = <62>;
+				clocks = <&clks IMX5_CLK_I2C1_GATE>;
+				status = "disabled";
+			};
 		};
 	};
 };

arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi

@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6dl-icore-mipi.dts

@@ -16,6 +16,5 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	status = "okay";
 };

arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"

arch/arm/dts/imx6dl-icore-u-boot.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"

arch/arm/dts/imx6dl-mamoj-u-boot.dtsi

@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6dl-mamoj.dts

@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 BTicino
+ * Copyright (C) 2018 Amarula Solutions B.V.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6dl.dtsi"
+
+/ {
+	model = "BTicino i.MX6DL Mamoj board";
+	compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "mii";
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "okay";
+
+	pmic: pfuze100@08 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			/* CPU vdd_arm core */
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* SOC vdd_soc */
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			/* I/O power GEN_3V3 */
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* DDR memory */
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* DDR memory */
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* not used */
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			/* not used */
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			/* PMIC vsnvs. EX boot mode */
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			/* not used */
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			/* not used */
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			/* not used */
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			/* 1v8 general power */
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			/* 2v8 general power IMX6 */
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			/* 3v3 Ethernet */
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b1
+			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+			MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2	0x1b0b0
+			MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3	0x1b0b0
+			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+			MX6QDL_PAD_GPIO_19__ENET_TX_ER		0x1b0b0
+			MX6QDL_PAD_GPIO_18__ENET_RX_CLK		0x1b0b1
+			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+			MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2	0x1b0b0
+			MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3      0x1b0b0
+			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+			MX6QDL_PAD_KEY_COL3__ENET_CRS		0x1b0b0
+			MX6QDL_PAD_KEY_ROW1__ENET_COL		0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
+			MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX6QDL_PAD_GPIO_7__I2C4_SCL	0x4001b8b1
+			MX6QDL_PAD_GPIO_8__I2C4_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_uart3: uart3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
+			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
+			MX6QDL_PAD_SD3_DAT4__SD3_DATA4	0x17059
+			MX6QDL_PAD_SD3_DAT5__SD3_DATA5	0x17059
+			MX6QDL_PAD_SD3_DAT6__SD3_DATA6	0x17059
+			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
+		>;
+	};
+};

arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi

@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6q-icore-mipi.dts

@@ -16,6 +16,5 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	status = "okay";
 };

arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-rqs-u-boot.dtsi"

arch/arm/dts/imx6q-icore-u-boot.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-icore-u-boot.dtsi"

arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi

@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&usdhc4 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc4 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6qdl-icore-rqs.dtsi

@@ -105,7 +105,6 @@
 };
 
 &usdhc3 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -114,7 +113,6 @@
 };
 
 &usdhc4 {
-	u-boot,dm-spl;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc4>;
 	pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
@@ -176,7 +174,6 @@
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
 			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
@@ -188,7 +185,6 @@
 	};
 
 	pinctrl_usdhc4: usdhc4grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
 			MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070

arch/arm/dts/imx6qdl-icore-u-boot.dtsi

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6qdl-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6qdl-icore.dtsi

@@ -122,7 +122,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -221,7 +220,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
@@ -233,7 +231,6 @@
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 			MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059

arch/arm/dts/imx6qdl-u-boot.dtsi

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+	soc {
+		u-boot,dm-spl;
+
+		aips-bus@02000000 {
+			u-boot,dm-spl;
+		};
+
+		aips-bus@02100000 {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6qdl.dtsi

@@ -77,7 +77,6 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
-		u-boot,dm-spl;
 
 		dma_apbh: dma-apbh@00110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
@@ -226,7 +225,6 @@
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			spba-bus@02000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
@@ -518,7 +516,6 @@
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-				u-boot,dm-spl;
 			};
 
 			gpio2: gpio@020a0000 {
@@ -808,7 +805,6 @@
 			iomuxc: iomuxc@020e0000 {
 				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 				reg = <0x020e0000 0x4000>;
-				u-boot,dm-spl;
 			};
 
 			ldb: ldb@020e0008 {
@@ -893,7 +889,6 @@
 			#size-cells = <1>;
 			reg = <0x02100000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			crypto: caam@2100000 {
 				compatible = "fsl,sec-v4.0";

arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi

@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	pinctrl_usdhc1: usdhc1grp {
+		u-boot,dm-spl;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		u-boot,dm-spl;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		u-boot,dm-spl;
+	};
+};

arch/arm/dts/imx6ul-geam-kit.dts

@@ -87,7 +87,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -135,7 +134,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
@@ -147,7 +145,6 @@
 	};
 
 	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
@@ -159,7 +156,6 @@
 	};
 
 	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9

arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi

@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6ul-isiot-u-boot.dtsi"
+
+&usdhc2 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6ul-isiot-emmc.dts

@@ -42,6 +42,7 @@
 
 /dts-v1/;
 
+#include "imx6ul.dtsi"
 #include "imx6ul-isiot.dtsi"
 
 / {
@@ -51,29 +52,5 @@
 
 &usdhc2 {
 	u-boot,dm-spl;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
-	bus-width = <8>;
-	no-1-8-v;
 	status = "okay";
 };
-
-&iomuxc {
-	pinctrl_usdhc2: usdhc2grp {
-		u-boot,dm-spl;
-		fsl,pins = <
-			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
-			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
-			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
-			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
-			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
-			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
-			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
-			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
-			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
-			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
-			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
-		>;
-	};
-};

arch/arm/dts/imx6ul-isiot-nand.dts

@@ -42,6 +42,7 @@
 
 /dts-v1/;
 
+#include "imx6ul.dtsi"
 #include "imx6ul-isiot.dtsi"
 
 / {

arch/arm/dts/imx6ul-isiot-u-boot.dtsi

@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include "imx6ul-u-boot.dtsi"
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6ul-isiot.dtsi

@@ -42,7 +42,6 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
-#include "imx6ul.dtsi"
 
 / {
 	memory {
@@ -82,7 +81,6 @@
 };
 
 &usdhc1 {
-	u-boot,dm-spl;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
@@ -91,6 +89,15 @@
 	status = "okay";
 };
 
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+	bus-width = <8>;
+	no-1-8-v;
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl_enet1: enet1grp {
 		fsl,pins = <
@@ -129,7 +136,6 @@
 	};
 
 	pinctrl_usdhc1: usdhc1grp {
-		u-boot,dm-spl;
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
 			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
@@ -139,4 +145,21 @@
 			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
 		>;
 	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		u-boot,dm-spl;
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
+			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
+		>;
+	};
 };

arch/arm/dts/imx6ul-u-boot.dtsi

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+	soc {
+		u-boot,dm-spl;
+	};
+};
+
+&aips1 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&aips2 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx6ul.dtsi

@@ -134,7 +134,6 @@
 		compatible = "simple-bus";
 		interrupt-parent = <&gpc>;
 		ranges;
-		u-boot,dm-spl;
 
 		pmu {
 			compatible = "arm,cortex-a7-pmu";
@@ -186,7 +185,6 @@
 			#size-cells = <1>;
 			reg = <0x02000000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			spba-bus@02000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
@@ -418,7 +416,6 @@
 				#interrupt-cells = <2>;
 				gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 					      <&iomuxc 16 33 16>;
-				u-boot,dm-spl;
 			};
 
 			gpio2: gpio@020a0000 {
@@ -455,7 +452,6 @@
 				interrupt-controller;
 				#interrupt-cells = <2>;
 				gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
-				u-boot,dm-spl;
 			};
 
 			gpio5: gpio@020ac000 {
@@ -654,7 +650,6 @@
 			iomuxc: iomuxc@020e0000 {
 				compatible = "fsl,imx6ul-iomuxc";
 				reg = <0x020e0000 0x4000>;
-				u-boot,dm-spl;
 			};
 
 			gpr: iomuxc-gpr@020e4000 {
@@ -735,7 +730,6 @@
 			#size-cells = <1>;
 			reg = <0x02100000 0x100000>;
 			ranges;
-			u-boot,dm-spl;
 
 			usbotg1: usb@02184000 {
 				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";

arch/arm/include/asm/arch-mx31/clock.h

@@ -9,17 +9,9 @@
 
 #include <common.h>
 
-#ifdef CONFIG_MX31_HCLK_FREQ
 #define MXC_HCLK	CONFIG_MX31_HCLK_FREQ
-#else
-#define MXC_HCLK	26000000
-#endif
 
-#ifdef CONFIG_MX31_CLK32
 #define MXC_CLK32	CONFIG_MX31_CLK32
-#else
-#define MXC_CLK32	32768
-#endif
 
 enum mxc_clock {
 	MXC_ARM_CLK,

arch/arm/mach-imx/mx3/Kconfig

@@ -0,0 +1,34 @@
+if ARCH_MX31
+
+config MX31
+       bool
+       default y
+choice
+	prompt "MX31 board select"
+	optional
+
+config TARGET_MX31PDK
+	bool "Support the i.MX31 PDK board from Freescale/NXP"
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select BOARD_EARLY_INIT_F
+
+endchoice
+
+config MX31_HCLK_FREQ
+       int "i.MX31 HCLK frequency"
+       default 26000000
+       help
+         Frequency in Hz of the high frequency input clock. Typically
+	 26000000 Hz.
+
+config MX31_CLK32
+       int "i.MX31 CLK32 Frequency"
+       default 32768
+       help
+         Frequency in Hz of the low frequency input clock. Typically
+	 32768 or 32000 Hz.
+
+source "board/freescale/mx31pdk/Kconfig"
+
+endif

arch/arm/mach-imx/mx5/Kconfig

@@ -16,6 +16,17 @@ choice
 	prompt "MX5 board select"
 	optional
 
+config TARGET_KP_IMX53
+	bool "Support K+P imx53 board"
+	select BOARD_LATE_INIT
+	select MX53
+	select DM
+	select DM_SERIAL
+	select DM_ETH
+	select DM_I2C
+	select DM_GPIO
+	select DM_PMIC
+
 config TARGET_M53EVK
 	bool "Support m53evk"
 	select MX53
@@ -79,6 +90,7 @@ source "board/freescale/mx53loco/Kconfig"
 source "board/freescale/mx53smd/Kconfig"
 source "board/ge/mx53ppd/Kconfig"
 source "board/inversepath/usbarmory/Kconfig"
+source "board/k+p/kp_imx53/Kconfig"
 source "board/technologic/ts4800/Kconfig"
 
 endif

arch/arm/mach-imx/mx6/Kconfig

@@ -5,6 +5,7 @@ config MX6_SMP
 	select ARM_ERRATA_761320
 	select ARM_ERRATA_794072
 	select ARM_ERRATA_845369
+	select MP
 	bool
 
 config MX6
@@ -167,18 +168,8 @@ config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 	select BOARD_LATE_INIT
 
-config TARGET_GE_B450V3
-	bool "General Electric B450v3"
-	select BOARD_LATE_INIT
-	select MX6Q
-
-config TARGET_GE_B650V3
-	bool "General Electric B650v3"
-	select BOARD_LATE_INIT
-	select MX6Q
-
-config TARGET_GE_B850V3
-	bool "General Electric B850v3"
+config TARGET_GE_BX50V3
+	bool "General Electric Bx50v3"
 	select BOARD_LATE_INIT
 	select MX6Q
 
@@ -229,6 +220,37 @@ config TARGET_MX6MEMCAL
 config TARGET_MX6QARM2
 	bool "mx6qarm2"
 
+config TARGET_MX6DL_MAMOJ
+	bool "Support BTicino Mamoj"
+	select MX6QDL
+	select OF_CONTROL
+	select PINCTRL
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_I2C
+	select DM_MMC
+	select DM_PMIC
+	select DM_PMIC_PFUZE100
+	select DM_THERMAL
+	select SPL
+	select SUPPORT_SPL
+	select SPL_DM if SPL
+	select SPL_OF_LIBFDT if SPL
+	select SPL_OF_CONTROL if SPL
+	select SPL_PINCTRL if SPL
+	select SPL_SEPARATE_BSS if SPL
+	select SPL_GPIO_SUPPORT if SPL
+	select SPL_LIBCOMMON_SUPPORT if SPL
+	select SPL_LIBDISK_SUPPORT if SPL
+	select SPL_LIBGENERIC_SUPPORT if SPL
+	select SPL_MMC_SUPPORT if SPL
+	select SPL_SERIAL_SUPPORT if SPL
+	select SPL_USB_HOST_SUPPORT if SPL
+	select SPL_USB_GADGET_SUPPORT if SPL
+	select SPL_USB_SDP_SUPPORT if SPL
+	select SPL_WATCHDOG_SUPPORT if SPL
+
 config TARGET_MX6Q_ENGICAM
 	bool "Support Engicam i.Core(RQS)"
 	select BOARD_LATE_INIT
@@ -472,6 +494,7 @@ source "board/bachmann/ot1200/Kconfig"
 source "board/barco/platinum/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
+source "board/bticino/mamoj/Kconfig"
 source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"

arch/sandbox/dts/sandbox.dts

@@ -115,6 +115,10 @@
 		sandbox_pmic: sandbox_pmic {
 			reg = <0x40>;
 		};
+
+		mc34708: pmic@41 {
+			reg = <0x41>;
+		};
 	};
 
 	lcd {

arch/sandbox/dts/sandbox64.dts

@@ -115,6 +115,10 @@
 		sandbox_pmic: sandbox_pmic {
 			reg = <0x40>;
 		};
+
+		mc34708: pmic@41 {
+			reg = <0x41>;
+		};
 	};
 
 	lcd {

arch/sandbox/dts/sandbox_pmic.dtsi

@@ -81,3 +81,36 @@
 		regulator-max-microvolt = <1500000>;
 	};
 };
+
+&mc34708 {
+	compatible = "fsl,mc34708";
+
+	pmic_emul {
+		compatible = "sandbox,i2c-pmic";
+
+		reg-defaults = /bits/ 8 <
+			0x00 0x80 0x08 0xff 0xff 0xff 0x2e 0x01 0x08
+			0x40 0x80 0x81 0x5f 0xff 0xfb 0x1e 0x80 0x18
+			0x00 0x00 0x0e 0x00 0x00 0x14 0x00 0x00 0x00
+			0x00 0x00 0x20 0x00 0x01 0x3a 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00
+			0x42 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x5f
+			0x01 0xff 0xff 0x00 0x00 0x00 0x00 0x7f 0xff
+			0x92 0x49 0x24 0x59 0x6d 0x34 0x18 0xc1 0x8c
+			0x00 0x60 0x18 0x51 0x48 0x45 0x14 0x51 0x45
+			0x00 0x06 0x32 0x00 0x00 0x00 0x06 0x9c 0x99
+			0x00 0x38 0x0a 0x00 0x38 0x0a 0x00 0x38 0x0a
+			0x00 0x38 0x0a 0x84 0x00 0x00 0x00 0x00 0x00
+			0x80 0x90 0x8f 0xf8 0x00 0x04 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x01 0x31 0x7e 0x2b 0x03 0xfd 0xc0 0x36 0x1b
+			0x60 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00
+		>;
+	};
+};

arch/sandbox/dts/test.dts

@@ -227,6 +227,10 @@
 		sandbox_pmic: sandbox_pmic {
 			reg = <0x40>;
 		};
+
+		mc34708: pmic@41 {
+			reg = <0x41>;
+		};
 	};
 
 	adc@0 {

board/bticino/mamoj/Kconfig

@@ -0,0 +1,12 @@
+if TARGET_MX6DL_MAMOJ
+
+config SYS_BOARD
+	default "mamoj"
+
+config SYS_VENDOR
+	default "bticino"
+
+config SYS_CONFIG_NAME
+	default "imx6dl-mamoj"
+
+endif

board/bticino/mamoj/MAINTAINERS

@@ -0,0 +1,10 @@
+MX6DL_MAMOJ BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+M:	Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+M:	Simone CIANNI <simone.cianni@bticino.it>
+S:	Maintained
+F:	board/bticino/mamoj
+F:	include/configs/imx6dl-mamoj.h
+F:	configs/imx6dl_mamoj_defconfig
+F:	arch/arm/dts/imx6dl-mamoj.dts
+F:	arch/arm/dts/imx6dl-mamoj-u-boot.dtsi

board/bticino/mamoj/Makefile

@@ -0,0 +1,8 @@
+# Copyright (C) 2018 BTicino
+# Copyright (C) 2017 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := mamoj.o
+obj-$(CONFIG_SPL_BUILD) += spl.o

board/bticino/mamoj/README

@@ -0,0 +1,124 @@
+BTicino Mamoj board:
+===================
+
+Build:
+
+ $ make mrproper
+ $ make imx6dl_mamoj_defconfig
+ $ make
+
+   This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+The following methods can be used for booting Mamoj boards:
+
+1. USB SDP boot
+
+2. eMMC boot (via DFU)
+
+3. Falcon mode
+
+1. USB SDP boot:
+---------------
+
+ - Build imx_usb_loader
+
+    $ git clone git://github.com/boundarydevices/imx_usb_loader.git
+    $ cd imx_usb_loader
+    $ make
+
+ - Build the BSP and copy SPL, u-boot-dtb.img in imx_usb_loader directory
+
+ - Put the board in "Serial Download Mode"
+
+ - Plug-in USB-to-Serial, Open minicom 1152008N1 and USB OTG cables to Host
+
+ - Turn-on board
+
+ - Identify VID/PID using lsusb
+
+    Bus 001 Device 010: ID 15a2:0061 Freescale Semiconductor, Inc. i.MX 6Solo/6DualLite SystemOnChip in RecoveryMode
+
+ - Update the conf files
+
+    imx_usb.conf
+      0x15a2:0x0061, mx6_usb_rom.conf, 0x0525:0xb4a4, mx6_usb_sdp_spl.conf
+
+    mx6_usb_rom.conf
+      mx6_usb
+      hid,1024,0x910000,0x10000000,512M,0x00900000,0x40000
+      SPL:jump header2
+
+    mx6_usb_sdp_spl.conf
+      mx6_spl_sdp
+      hid,uboot_header,1024,0x910000,0x10000000,512M,0x00900000,0x40000
+      u-boot-dtb.img:jump header2
+
+  - Launch the loader
+
+     $ ./imx_usb
+
+  We can see U-Boot boot from USB SDP on minicom
+
+2. eMMC boot via DFU:
+--------------------
+
+  Once booted from USB SDP, program the eMMC as below(make sure to connect USB OTG)
+
+  - Change eMMC partition config
+
+     => mmc partconf 2 1 0 0
+
+  - Partition eMMC on host
+
+     => ums 0 mmc 2
+
+    Host will able to detect the eMMC disk as UMS, partition the same.
+
+  - Program SPL
+
+     => setenv dfu_alt_info $dfu_alt_info_spl
+     => dfu 0 mmc 2
+
+     At Host
+
+     # dfu-util -D SPL -a spl
+
+  - Program u-boot-dtb.img
+
+     => setenv dfu_alt_info $dfu_alt_info_uboot
+     => dfu 0 mmc 2
+
+     At Host
+
+     # dfu-util -D u-boot-dtb.img -a u-boot
+
+  Poweroff and Poweron the board and see U-Boot booting from eMMC.
+
+3. Falcon mode:
+--------------
+
+  - Skip 10M space and create dual partitions for eMMC, start sector is 20480
+
+    Partition Map for MMC device 2  --   Partition Type: DOS
+
+    Part    Start Sector    Num Sectors     UUID            Type
+      1     20480           131072          c52e78be-01     83
+      2     151552          7581696         c52e78be-02     83
+
+  - Write uImage
+
+    => fatload mmc 2:1 $kernel_addr_r uImage
+    => mmc write $kernel_addr_r 0x1000 0x4000
+
+  - Write dtb and args
+
+    => setenv bootargs console=ttymxc2,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw quiet
+    => fatload mmc 2:1 $fdt_addr_r imx6dl-mamoj.dtb
+    => spl export fdt $kernel_addr_r - $fdt_addr_r
+    => mmc write 0x13000000 0x800 0x800
+
+  Poweroff and Poweron the board and see Linux booting directly after SPL.
+
+--
+Jagan Teki <jagan@amarulasolutions.com>
+03/12/18

board/bticino/mamoj/mamoj.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}

board/bticino/mamoj/spl.c

@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	return 0;
+}
+#endif
+
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 32,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0042004b,
+	.p0_mpwldectrl1 = 0x0038003c,
+	.p0_mpdgctrl0 = 0x42340230,
+	.p0_mpdgctrl1 = 0x0228022c,
+	.p0_mprddlctl = 0x42444646,
+	.p0_mpwrdlctl = 0x38382e2e,
+};
+
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+	.refsel		= 1,
+	.refr		= 7,
+};
+
+static void spl_dram_init(void)
+{
+	mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+	mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
+
+	udelay(100);
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00003f3f, &ccm->CCGR0);
+	writel(0x0030fc00, &ccm->CCGR1);
+	writel(0x000fc000, &ccm->CCGR2);
+	writel(0x3f300000, &ccm->CCGR3);
+	writel(0xff00f300, &ccm->CCGR4);
+	writel(0x0f0000c3, &ccm->CCGR5);
+	writel(0x000003cc, &ccm->CCGR6);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	SETUP_IOMUX_PADS(uart3_pads);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+}

board/engicam/imx6q/MAINTAINERS

@@ -9,12 +9,21 @@ F:	configs/imx6dl_icore_nand_defconfig
 F:	configs/imx6qdl_icore_rqs_defconfig
 F:	configs/imx6qdl_icore_mipi_defconfig
 F:	configs/imx6qdl_icore_nand_defconfig
+F:	arch/arm/dts/imx6qdl.dtsi
+F:	arch/arm/dts/imx6qdl-u-boot.dtsi
 F:	arch/arm/dts/imx6qdl-icore.dtsi
+F:	arch/arm/dts/imx6qdl-icore-u-boot.dtsi
 F:	arch/arm/dts/imx6q-icore.dts
+F:	arch/arm/dts/imx6q-icore-u-boot.dtsi
 F:	arch/arm/dts/imx6dl-icore.dts
+F:	arch/arm/dts/imx6dl-icore-u-boot.dtsi
 F:	arch/arm/dts/imx6qdl-icore-rqs.dtsi
+F:	arch/arm/dts/imx6qdl-icore-rqs-u-boot.dtsi
 F:	arch/arm/dts/imx6q-icore-rqs.dts
+F:	arch/arm/dts/imx6q-icore-rqs-u-boot.dtsi
 F:	arch/arm/dts/imx6dl-icore-rqs.dts
+F:	arch/arm/dts/imx6dl-icore-rqs-u-boot.dtsi
 F:	arch/arm/dts/imx6dl-icore-mipi.dts
+F:	arch/arm/dts/imx6dl-icore-mipi-u-boot.dtsi
 F:	arch/arm/dts/imx6q-icore-mipi.dts
-F:	arch/arm/dts/imx6qdl-icore.dtsi
+F:	arch/arm/dts/imx6q-icore-mipi-u-boot.dtsi

board/engicam/imx6ul/MAINTAINERS

@@ -8,7 +8,12 @@ F:	configs/imx6ul_geam_nand_defconfig
 F:	configs/imx6ul_isiot_emmc_defconfig
 F:	configs/imx6ul_isiot_mmc_defconfig
 F:	configs/imx6ul_isiot_nand_defconfig
+F:	arch/arm/dts/imx6ul.dtsi
+F:	arch/arm/dts/imx6ul-u-boot.dtsi
 F:	arch/arm/dts/imx6ul-geam-kit.dts
+F:	arch/arm/dts/imx6ul-geam-kit-u-boot.dtsi
 F:	arch/arm/dts/imx6ul-isiot.dtsi
+F:	arch/arm/dts/imx6ul-isiot-u-boot.dtsi
 F:	arch/arm/dts/imx6ul-isiot-emmc.dts
+F:	arch/arm/dts/imx6ul-isiot-emmc-u-boot.dtsi
 F:	arch/arm/dts/imx6ul-isiot-nand.dts

board/ge/bx50v3/Kconfig

@@ -1,4 +1,4 @@
-if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
+if TARGET_GE_BX50V3
 
 config IMX_CONFIG
 	default "board/ge/bx50v3/bx50v3.cfg"

board/ge/bx50v3/bx50v3.c

@@ -33,6 +33,11 @@
 #include "../../../drivers/net/e1000.h"
 DECLARE_GLOBAL_DATA_PTR;
 
+struct vpd_cache;
+
+static int confidx = 3;  /* Default to b850v3. */
+static struct vpd_cache vpd;
+
 #ifndef CONFIG_SYS_I2C_EEPROM_ADDR
 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50
 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
@@ -361,20 +366,21 @@ int board_cfb_skip(void)
 	return 0;
 }
 
-static int detect_baseboard(struct display_info_t const *dev)
+static int is_b850v3(void)
 {
-	if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
-	    IS_ENABLED(CONFIG_TARGET_GE_B650V3))
-		return 1;
+	return confidx == 3;
+}
 
-	return 0;
+static int detect_lcd(struct display_info_t const *dev)
+{
+	return !is_b850v3();
 }
 
 struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= -1,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_baseboard,
+	.detect	= detect_lcd,
 	.enable	= NULL,
 	.mode	= {
 		.name           = "G121X1-L03",
@@ -492,6 +498,8 @@ static void setup_display_bx50v3(void)
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
+	enable_videopll();
+
 	/* When a reset/reboot is performed the display power needs to be turned
 	 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
 	 * an additional 200ms here. Unfortunately we use external PMIC for
@@ -593,23 +601,16 @@ static void process_vpd(struct vpd_cache *vpd)
 	switch (vpd->product_id) {
 	case VPD_PRODUCT_B450:
 		env_set("confidx", "1");
+		i210_index = 0;
+		fec_index = 1;
 		break;
 	case VPD_PRODUCT_B650:
 		env_set("confidx", "2");
-		break;
-	case VPD_PRODUCT_B850:
-		env_set("confidx", "3");
-		break;
-	}
-
-	switch (vpd->product_id) {
-	case VPD_PRODUCT_B450:
-		/* fall thru */
-	case VPD_PRODUCT_B650:
 		i210_index = 0;
 		fec_index = 1;
 		break;
 	case VPD_PRODUCT_B850:
+		env_set("confidx", "3");
 		i210_index = 1;
 		fec_index = 2;
 		break;
@@ -624,7 +625,6 @@ static void process_vpd(struct vpd_cache *vpd)
 
 static int read_vpd(uint eeprom_bus)
 {
-	struct vpd_cache vpd;
 	int res;
 	int size = 1024;
 	uint8_t *data;
@@ -644,7 +644,6 @@ static int read_vpd(uint eeprom_bus)
 	if (res == 0) {
 		memset(&vpd, 0, sizeof(vpd));
 		vpd_reader(size, data, &vpd, vpd_callback);
-		process_vpd(&vpd);
 	}
 
 	free(data);
@@ -684,7 +683,7 @@ int board_early_init_f(void)
 	setup_iomux_uart();
 
 #if defined(CONFIG_VIDEO_IPUV3)
-	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+	if (is_b850v3())
 		/* Set LDB clock to Video PLL */
 		select_ldb_di_clock_source(MXC_PLL5_CLK);
 	else
@@ -694,12 +693,35 @@ int board_early_init_f(void)
 	return 0;
 }
 
+static void set_confidx(const struct vpd_cache* vpd)
+{
+	switch (vpd->product_id) {
+	case VPD_PRODUCT_B450:
+		confidx = 1;
+		break;
+	case VPD_PRODUCT_B650:
+		confidx = 2;
+		break;
+	case VPD_PRODUCT_B850:
+		confidx = 3;
+		break;
+	}
+}
+
 int board_init(void)
 {
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+	read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
+
+	set_confidx(&vpd);
+
 	gpio_direction_output(SUS_S3_OUT, 1);
 	gpio_direction_output(WIFI_EN, 1);
 #if defined(CONFIG_VIDEO_IPUV3)
-	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+	if (is_b850v3())
 		setup_display_b850v3();
 	else
 		setup_display_bx50v3();
@@ -710,10 +732,6 @@ int board_init(void)
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
 	return 0;
 }
 
@@ -779,12 +797,15 @@ void pmic_init(void)
 
 int board_late_init(void)
 {
-	read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
+	process_vpd(&vpd);
 
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
 
+	if (is_b850v3())
+		env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
+
 	/* board specific pmic init */
 	pmic_init();
 

board/k+p/kp_imx53/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_KP_IMX53
+
+config SYS_BOARD
+	default "kp_imx53"
+
+config SYS_VENDOR
+	default "k+p"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "kp_imx53"
+
+endif

board/k+p/kp_imx53/MAINTAINERS

@@ -0,0 +1,6 @@
+KP_IMX53_HSC BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/k+p/kp_imx53/
+F:	include/configs/kp_imx53.h
+F:	configs/kp_imx53_defconfig

board/k+p/kp_imx53/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2018, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+
+obj-y		+= kp_imx53.o kp_id_rev.o

board/k+p/kp_imx53/kp_id_rev.c

@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <i2c.h>
+#include "kp_id_rev.h"
+
+static int eeprom_has_been_read;
+static struct id_eeprom eeprom;
+
+void show_eeprom(void)
+{
+	char safe_string[33];
+	int i;
+	u8 *p;
+
+	puts("Module EEPROM:\n");
+	/* ID */
+	for (i = 0; i <= sizeof(eeprom.id) && 0xff != eeprom.id[i]; ++i)
+		safe_string[i] = eeprom.id[i];
+	safe_string[i] = '\0';
+
+	if (!strncmp(safe_string, "TQM", 3)) {
+		printf("  ID: %s\n", safe_string);
+		env_set("boardtype", safe_string);
+	} else {
+		puts("  unknown hardware variant\n");
+	}
+
+	/* Serial number */
+	for (i = 0; (sizeof(eeprom.serial) >= i) &&
+		    (eeprom.serial[i] >= 0x30) &&
+		    (eeprom.serial[i] <= 0x39); ++i)
+		safe_string[i] = eeprom.serial[i];
+	safe_string[i] = '\0';
+
+	if (strlen(safe_string) == 8) {
+		printf("  SN: %s\n", safe_string);
+		env_set("serial#", safe_string);
+	} else {
+		puts("  unknown serial number\n");
+	}
+
+	/* MAC address  */
+	p = eeprom.mac;
+	if (!is_valid_ethaddr(p)) {
+		printf("  Not valid ETH EEPROM addr!\n");
+		return;
+	}
+
+	printf("  MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+	       p[0], p[1], p[2], p[3], p[4], p[5]);
+
+	eth_env_set_enetaddr("ethaddr", p);
+}
+
+int read_eeprom(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (eeprom_has_been_read)
+		return 0;
+
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
+	if (ret) {
+		printf("Cannot find EEPROM !\n");
+		return ret;
+	}
+
+	ret = dm_i2c_read(dev, 0x0, (uchar *)&eeprom, sizeof(eeprom));
+
+	eeprom_has_been_read = (ret == 0) ? 1 : 0;
+	return ret;
+}
+
+int read_board_id(void)
+{
+	unsigned char rev_id = 0x42;
+	char rev_str[32], buf[8];
+	struct udevice *dev;
+	int ret;
+
+	ret = i2c_get_chip_for_busnum(2, 0x22, 1, &dev);
+	if (ret) {
+		printf("Cannot find pcf8574 IO expander !\n");
+		return ret;
+	}
+
+	dm_i2c_read(dev, 0x0, &rev_id, sizeof(rev_id));
+
+	sprintf(rev_str, "%02X", rev_id);
+	if (rev_id & 0x80) {
+		printf("BBoard:4x00 Rev:%s\n", rev_str);
+		env_set("boardtype", "ddc");
+		env_set("fit_config", "imx53_kb_conf");
+	} else {
+		printf("BBoard:40x0 Rev:%s\n", rev_str);
+		env_set("boardtype", "hsc");
+		env_set("fit_config", "imx53_kb_40x0_conf");
+	}
+
+	sprintf(buf, "kp-%s", env_get("boardtype"));
+	env_set("boardname", buf);
+	env_set("boardsoc", "imx53");
+	env_set("kb53_rev", rev_str);
+
+	return 0;
+}

board/k+p/kp_imx53/kp_id_rev.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Based on code developed by:
+ *
+ * Copyright (C) 2012 TQ-Systems GmbH
+ * Daniel Gericke <daniel.gericke@tqs.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __KP_ID_REV_H_
+#define __KP_ID_REV_H_
+
+struct id_eeprom {
+	u8 hrcw_primary[0x20];
+	u8 mac[6];              /* 0x20 ... 0x25 */
+	u8 rsv1[10];
+	u8 serial[8];           /* 0x30 ... 0x37 */
+	u8 rsv2[8];
+	u8 id[0x40];            /* 0x40 ... 0x7f */
+} __packed;
+
+void show_eeprom(void);
+int read_eeprom(void);
+int read_board_id(void);
+#endif /* __KP_ID_REV_H_ */

board/k+p/kp_imx53/kp_imx53.c

@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/gpio.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include "kp_id_rev.h"
+
+#define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
+#define PHY_nRST IMX_GPIO_NR(7, 6)
+#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	u32 size;
+
+	size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	gd->ram_size = size;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+	gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN");
+	gpio_direction_output(VBUS_PWR_EN, 1);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[] = {
+	{MMC_SDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1; /* eMMC is always present */
+}
+
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	static const iomux_v3_cfg_t sd3_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+			     SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
+	};
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads));
+
+	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
+static int power_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("mc34708", &dev);
+	if (ret) {
+		printf("%s: mc34708 not found !\n", __func__);
+		return ret;
+	}
+
+	/* Set VDDGP to 1.110V for 800 MHz on SW1 */
+	pmic_clrsetbits(dev, REG_SW_0, SWx_VOLT_MASK_MC34708,
+			SWx_1_110V_MC34708);
+
+	/* Set VCC as 1.30V on SW2 */
+	pmic_clrsetbits(dev, REG_SW_1, SWx_VOLT_MASK_MC34708,
+			SWx_1_300V_MC34708);
+
+	/* Set global reset timer to 4s */
+	pmic_clrsetbits(dev, REG_POWER_CTL2, TIMER_MASK_MC34708,
+			TIMER_4S_MC34708);
+
+	return ret;
+}
+
+static void setup_clocks(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * CPU clock set to 800MHz and DDR to 400MHz
+	 */
+	ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 800MHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+static void setup_ups(void)
+{
+	gpio_request(BOOSTER_OFF, "BOOSTER_OFF");
+	gpio_direction_output(BOOSTER_OFF, 0);
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+void eth_phy_reset(void)
+{
+	gpio_request(PHY_nRST, "PHY_nRST");
+	gpio_direction_output(PHY_nRST, 1);
+	udelay(50);
+	gpio_set_value(PHY_nRST, 0);
+	udelay(400);
+	gpio_set_value(PHY_nRST, 1);
+	udelay(50);
+}
+
+int board_late_init(void)
+{
+	int ret = 0;
+
+	setup_ups();
+
+	if (!power_init())
+		setup_clocks();
+
+	ret = read_eeprom();
+	if (ret)
+		printf("Error %d reading EEPROM content!\n", ret);
+
+	eth_phy_reset();
+
+	show_eeprom();
+	read_board_id();
+
+	return ret;
+}

cmd/pmic.c

@@ -75,8 +75,9 @@ static int do_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+	struct uc_pmic_priv *priv;
 	struct udevice *dev;
-	uint8_t value;
+	char fmt[16];
 	uint reg;
 	int ret;
 
@@ -86,12 +87,15 @@ static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 
 	dev = currdev;
-
+	priv = dev_get_uclass_priv(dev);
 	printf("Dump pmic: %s registers\n", dev->name);
 
+	sprintf(fmt, "%%%d.%dx ", priv->trans_len * 2,
+		priv->trans_len * 2);
+
 	for (reg = 0; reg < pmic_reg_count(dev); reg++) {
-		ret = pmic_read(dev, reg, &value, 1);
-		if (ret) {
+		ret = pmic_reg_read(dev, reg);
+		if (ret < 0) {
 			printf("Can't read register: %d\n", reg);
 			return failure(ret);
 		}
@@ -99,7 +103,7 @@ static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		if (!(reg % 16))
 			printf("\n0x%02x: ", reg);
 
-		printf("%2.2x ", value);
+		printf(fmt, ret);
 	}
 	printf("\n");
 
@@ -108,9 +112,10 @@ static int do_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 static int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+	struct uc_pmic_priv *priv;
 	struct udevice *dev;
 	int regs, ret;
-	uint8_t value;
+	char fmt[24];
 	uint reg;
 
 	if (!currdev) {
@@ -119,6 +124,7 @@ static int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 
 	dev = currdev;
+	priv = dev_get_uclass_priv(dev);
 
 	if (argc != 2)
 		return CMD_RET_USAGE;
@@ -130,13 +136,15 @@ static int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return failure(-EFAULT);
 	}
 
-	ret = pmic_read(dev, reg, &value, 1);
-	if (ret) {
+	ret = pmic_reg_read(dev, reg);
+	if (ret < 0) {
 		printf("Can't read PMIC register: %d!\n", reg);
 		return failure(ret);
 	}
 
-	printf("0x%02x: 0x%2.2x\n", reg, value);
+	sprintf(fmt, "0x%%02x: 0x%%%d.%dx\n", priv->trans_len * 2,
+		priv->trans_len * 2);
+	printf(fmt, reg, ret);
 
 	return CMD_RET_SUCCESS;
 }
@@ -144,9 +152,8 @@ static int do_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 static int do_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	struct udevice *dev;
+	uint reg, value;
 	int regs, ret;
-	uint8_t value;
-	uint reg;
 
 	if (!currdev) {
 		printf("First, set the PMIC device!\n");
@@ -167,7 +174,7 @@ static int do_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	value = simple_strtoul(argv[2], NULL, 0);
 
-	ret = pmic_write(dev, reg, &value, 1);
+	ret = pmic_reg_write(dev, reg, value);
 	if (ret) {
 		printf("Can't write PMIC register: %d!\n", reg);
 		return failure(ret);

configs/ge_b650v3_defconfig

@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_GE_B650V3=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="imx6q-b650v3.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_EXT=y
-CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_CMD_E1000=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set

configs/ge_b850v3_defconfig

@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_GE_B850V3=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_FIT=y
-CONFIG_BOOTDELAY=1
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="imx6q-b850v3.dtb"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_LAST_STAGE_INIT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_NFS is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_BOOTCOUNT_EXT=y
-CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5"
-CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000
-CONFIG_FSL_ESDHC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_NETDEVICES=y
-CONFIG_E1000=y
-CONFIG_CMD_E1000=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
-CONFIG_OF_LIBFDT=y
-# CONFIG_EFI_LOADER is not set

configs/ge_b450v3_defconfig → configs/ge_bx50v3_defconfig

@@ -1,14 +1,13 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
-CONFIG_TARGET_GE_B450V3=y
+CONFIG_TARGET_GE_BX50V3=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_BOOTDELAY=1
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DEFAULT_FDT_FILE="imx6q-b450v3.dtb"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_HUSH_PARSER=y
@@ -41,3 +40,4 @@ CONFIG_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set
+CONFIG_SPI_FLASH_WINBOND=y

configs/imx6dl_mamoj_defconfig

@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_MX6DL_MAMOJ=y
+CONFIG_SPL_OS_BOOT=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mamoj"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_SYS_PROMPT="=> "
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_FEC_MXC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_DFU_MMC=y
+CONFIG_IMX_THERMAL=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SECURE_BOOT=y

configs/kp_imx53_defconfig

@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_SYS_TEXT_BASE=0x77800000
+CONFIG_TARGET_KP_IMX53=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx53-kp"
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR=1
+CONFIG_PHY_SMSC=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX5=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_DM_PMIC_MC34708=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=2
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y

configs/mx31pdk_defconfig

@@ -1,9 +1,10 @@
 CONFIG_ARM=y
 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
 # CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_TARGET_MX31PDK=y
+CONFIG_ARCH_MX31=y
 CONFIG_SYS_TEXT_BASE=0x87e00000
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_MX31PDK=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL=y

configs/mx53ppd_defconfig

@@ -22,6 +22,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_MMC=y
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_EXT=y
 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"

configs/mx6qsabrelite_defconfig

@@ -3,36 +3,31 @@ CONFIG_ARCH_MX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
 CONFIG_BOOTDELAY=3
+# CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
-CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_HUSH_PARSER=y
 CONFIG_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SATA=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
+# CONFIG_ISO_PARTITION is not set
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y

configs/sandbox_defconfig

@@ -142,6 +142,7 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_PMIC_MAX77686=y
+CONFIG_DM_PMIC_MC34708=y
 CONFIG_PMIC_PM8916=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_PMIC_S2MPS11=y

configs/sandbox_flattree_defconfig

@@ -125,6 +125,7 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_PMIC_MAX77686=y
+CONFIG_DM_PMIC_MC34708=y
 CONFIG_PMIC_PM8916=y
 CONFIG_PMIC_S2MPS11=y
 CONFIG_DM_PMIC_SANDBOX=y

configs/sandbox_spl_defconfig

@@ -141,6 +141,7 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_ACT8846=y
 CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_PMIC_MAX77686=y
+CONFIG_DM_PMIC_MC34708=y
 CONFIG_PMIC_PM8916=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_PMIC_S2MPS11=y

drivers/power/pmic/Kconfig

@@ -69,6 +69,13 @@ config DM_PMIC_MAX8998
 	This config enables implementation of driver-model pmic uclass features
 	for PMIC MAX8998. The driver implements read/write operations.
 
+config DM_PMIC_MC34708
+	bool "Enable Driver Model for PMIC MC34708"
+	depends on DM_PMIC
+	help
+	 This config enables implementation of driver-model pmic uclass features
+	 for PMIC MC34708. The driver implements read/write operations.
+
 config PMIC_MAX8997
 	bool "Enable Driver Model for PMIC MAX8997"
 	depends on DM_PMIC

drivers/power/pmic/Makefile

@@ -6,6 +6,7 @@
 obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
+obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
 obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o

drivers/power/pmic/i2c_pmic_emul.c

@@ -18,8 +18,11 @@
  * @reg:    PMICs registers array
  */
 struct sandbox_i2c_pmic_plat_data {
-	u8 rw_reg;
-	u8 reg[SANDBOX_PMIC_REG_COUNT];
+	u8 rw_reg, rw_idx;
+	u8 reg_count;
+	u8 trans_len;
+	u8 buf_size;
+	u8 *reg;
 };
 
 static int sandbox_i2c_pmic_read_data(struct udevice *emul, uchar chip,
@@ -27,16 +30,16 @@ static int sandbox_i2c_pmic_read_data(struct udevice *emul, uchar chip,
 {
 	struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
 
-	if (plat->rw_reg + len > SANDBOX_PMIC_REG_COUNT) {
+	if (plat->rw_idx + len > plat->buf_size) {
 		pr_err("Request exceeds PMIC register range! Max register: %#x",
-		      SANDBOX_PMIC_REG_COUNT);
+		      plat->reg_count);
 		return -EFAULT;
 	}
 
-	debug("Read PMIC: %#x at register: %#x count: %d\n",
-	      (unsigned)chip & 0xff, plat->rw_reg, len);
+	debug("Read PMIC: %#x at register: %#x idx: %#x count: %d\n",
+	      (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len);
 
-	memcpy(buffer, &plat->reg[plat->rw_reg], len);
+	memcpy(buffer, plat->reg + plat->rw_idx, len);
 
 	return 0;
 }
@@ -53,9 +56,10 @@ static int sandbox_i2c_pmic_write_data(struct udevice *emul, uchar chip,
 
 	/* Set PMIC register for I/O */
 	plat->rw_reg = *buffer;
+	plat->rw_idx = plat->rw_reg * plat->trans_len;
 
-	debug("Write PMIC: %#x at register: %#x count: %d\n",
-	      (unsigned)chip & 0xff, plat->rw_reg, len);
+	debug("Write PMIC: %#x at register: %#x idx: %#x count: %d\n",
+	      (unsigned int)chip & 0xff, plat->rw_reg, plat->rw_idx, len);
 
 	/* For read operation, set (write) only chip reg */
 	if (next_is_read)
@@ -64,12 +68,12 @@ static int sandbox_i2c_pmic_write_data(struct udevice *emul, uchar chip,
 	buffer++;
 	len--;
 
-	if (plat->rw_reg + len > SANDBOX_PMIC_REG_COUNT) {
+	if (plat->rw_idx + len > plat->buf_size) {
 		pr_err("Request exceeds PMIC register range! Max register: %#x",
-		      SANDBOX_PMIC_REG_COUNT);
+		      plat->reg_count);
 	}
 
-	memcpy(&plat->reg[plat->rw_reg], buffer, len);
+	memcpy(plat->reg + plat->rw_idx, buffer, len);
 
 	return 0;
 }
@@ -100,20 +104,33 @@ static int sandbox_i2c_pmic_xfer(struct udevice *emul, struct i2c_msg *msg,
 static int sandbox_i2c_pmic_ofdata_to_platdata(struct udevice *emul)
 {
 	struct sandbox_i2c_pmic_plat_data *plat = dev_get_platdata(emul);
+	struct udevice *pmic_dev = dev_get_parent(emul);
+	struct uc_pmic_priv *priv = dev_get_uclass_priv(pmic_dev);
 	const u8 *reg_defaults;
 
 	debug("%s:%d Setting PMIC default registers\n", __func__, __LINE__);
+	plat->reg_count = pmic_reg_count(pmic_dev);
+	plat->trans_len = priv->trans_len;
+	plat->buf_size = plat->reg_count * plat->trans_len;
+
+	plat->reg = calloc(1, plat->buf_size);
+	if (!plat->reg) {
+		debug("Canot allocate memory (%d B) for PMIC I2C emulation!\n",
+		      plat->buf_size);
+		return -ENOMEM;
+	}
 
 	reg_defaults = dev_read_u8_array_ptr(emul, "reg-defaults",
-					     SANDBOX_PMIC_REG_COUNT);
+					     plat->buf_size);
 
 	if (!reg_defaults) {
 		pr_err("Property \"reg-defaults\" not found for device: %s!",
 		      emul->name);
+		free(plat->reg);
 		return -EINVAL;
 	}
 
-	memcpy(&plat->reg, reg_defaults, SANDBOX_PMIC_REG_COUNT);
+	memcpy(plat->reg, reg_defaults, plat->buf_size);
 
 	return 0;
 }

drivers/power/pmic/mc34708.c

@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fsl_pmic.h>
+#include <i2c.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int mc34708_reg_count(struct udevice *dev)
+{
+	return PMIC_NUM_OF_REGS;
+}
+
+static int mc34708_write(struct udevice *dev, uint reg, const u8 *buff,
+			 int len)
+{
+	u8 buf[3] = { 0 };
+	int ret;
+
+	if (len != MC34708_TRANSFER_SIZE)
+		return -EINVAL;
+
+	/*
+	 * The MC34708 sends data with big endian format, hence we need to
+	 * perform manual byte swap.
+	 */
+	buf[0] = buff[2];
+	buf[1] = buff[1];
+	buf[2] = buff[0];
+
+	ret = dm_i2c_write(dev, reg, buf, len);
+	if (ret)
+		printf("write error to device: %p register: %#x!", dev, reg);
+
+	return ret;
+}
+
+static int mc34708_read(struct udevice *dev, uint reg, u8 *buff, int len)
+{
+	u8 buf[3] = { 0 };
+	int ret;
+
+	if (len != MC34708_TRANSFER_SIZE)
+		return -EINVAL;
+
+	ret = dm_i2c_read(dev, reg, buf, len);
+	if (ret)
+		printf("read error from device: %p register: %#x!", dev, reg);
+
+	buff[0] = buf[2];
+	buff[1] = buf[1];
+	buff[2] = buf[0];
+
+	return ret;
+}
+
+static int mc34708_probe(struct udevice *dev)
+{
+	struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
+
+	priv->trans_len = MC34708_TRANSFER_SIZE;
+
+	/*
+	 * Handle PMIC Errata 37: APS mode not fully functional,
+	 * use explicit PWM or PFM instead
+	 */
+	pmic_clrsetbits(dev, MC34708_REG_SW12_OPMODE,
+			MC34708_SW1AMODE_MASK | MC34708_SW2MODE_MASK,
+			SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 14u));
+
+	pmic_clrsetbits(dev, MC34708_REG_SW345_OPMODE,
+			MC34708_SW3MODE_MASK | MC34708_SW4AMODE_MASK |
+			MC34708_SW4BMODE_MASK | MC34708_SW5MODE_MASK,
+			SW_MODE_PWMPWM | (SW_MODE_PWMPWM << 6u) |
+			(SW_MODE_PWMPWM << 12u) | (SW_MODE_PWMPWM << 18u));
+
+	return 0;
+}
+
+static struct dm_pmic_ops mc34708_ops = {
+	.reg_count = mc34708_reg_count,
+	.read	= mc34708_read,
+	.write	= mc34708_write,
+};
+
+static const struct udevice_id mc34708_ids[] = {
+	{ .compatible = "fsl,mc34708" },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_mc34708) = {
+	.name		= "mc34708_pmic",
+	.id		= UCLASS_PMIC,
+	.of_match	= mc34708_ids,
+	.probe          = mc34708_probe,
+	.ops		= &mc34708_ops,
+};

drivers/power/pmic/pmic-uclass.c

@@ -130,23 +130,35 @@ int pmic_write(struct udevice *dev, uint reg, const uint8_t *buffer, int len)
 
 int pmic_reg_read(struct udevice *dev, uint reg)
 {
-	u8 byte;
+	struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
+	u32 val = 0;
 	int ret;
 
-	debug("%s: reg=%x", __func__, reg);
-	ret = pmic_read(dev, reg, &byte, 1);
-	debug(", value=%x, ret=%d\n", byte, ret);
+	if (priv->trans_len < 1 || priv->trans_len > sizeof(val)) {
+		debug("Wrong transmission size [%d]\n", priv->trans_len);
+		return -EINVAL;
+	}
+
+	debug("%s: reg=%x priv->trans_len:%d", __func__, reg, priv->trans_len);
+	ret = pmic_read(dev, reg, (uint8_t *)&val, priv->trans_len);
+	debug(", value=%x, ret=%d\n", val, ret);
 
-	return ret ? ret : byte;
+	return ret ? ret : val;
 }
 
 int pmic_reg_write(struct udevice *dev, uint reg, uint value)
 {
-	u8 byte = value;
+	struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
 	int ret;
 
-	debug("%s: reg=%x, value=%x", __func__, reg, value);
-	ret = pmic_write(dev, reg, &byte, 1);
+	if (priv->trans_len < 1 || priv->trans_len > sizeof(value)) {
+		debug("Wrong transmission size [%d]\n", priv->trans_len);
+		return -EINVAL;
+	}
+
+	debug("%s: reg=%x, value=%x priv->trans_len:%d", __func__, reg, value,
+	      priv->trans_len);
+	ret = pmic_write(dev, reg, (uint8_t *)&value, priv->trans_len);
 	debug(", ret=%d\n", ret);
 
 	return ret;
@@ -154,18 +166,34 @@ int pmic_reg_write(struct udevice *dev, uint reg, uint value)
 
 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
 {
-	u8 byte;
+	struct uc_pmic_priv *priv = dev_get_uclass_priv(dev);
+	u32 val = 0;
 	int ret;
 
-	ret = pmic_reg_read(dev, reg);
+	if (priv->trans_len < 1 || priv->trans_len > sizeof(val)) {
+		debug("Wrong transmission size [%d]\n", priv->trans_len);
+		return -EINVAL;
+	}
+
+	ret = pmic_read(dev, reg, (uint8_t *)&val, priv->trans_len);
 	if (ret < 0)
 		return ret;
-	byte = (ret & ~clr) | set;
 
-	return pmic_reg_write(dev, reg, byte);
+	val = (val & ~clr) | set;
+	return pmic_write(dev, reg, (uint8_t *)&val, priv->trans_len);
+}
+
+static int pmic_pre_probe(struct udevice *dev)
+{
+	struct uc_pmic_priv *pmic_priv = dev_get_uclass_priv(dev);
+
+	pmic_priv->trans_len = 1;
+	return 0;
 }
 
 UCLASS_DRIVER(pmic) = {
 	.id		= UCLASS_PMIC,
 	.name		= "pmic",
+	.pre_probe	= pmic_pre_probe,
+	.per_device_auto_alloc_size = sizeof(struct uc_pmic_priv),
 };

include/configs/advantech_dms-ba16.h

@@ -45,7 +45,6 @@
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_BOUNCE_BUFFER
 
 /* USB Configs */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2

include/configs/apalis_imx6.h

@@ -56,7 +56,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
-#define CONFIG_BOUNCE_BUFFER
 
 /*
  * SATA Configs

include/configs/colibri_imx6.h

@@ -54,7 +54,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
-#define CONFIG_BOUNCE_BUFFER
 
 /* Network */
 #define CONFIG_FEC_MXC

include/configs/dh_imx6.h

@@ -33,7 +33,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_BOUNCE_BUFFER
 #define CONFIG_BZIP2
 
 /* Size of malloc() pool */

include/configs/ge_bx50v3.h

@@ -14,19 +14,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/mach-imx/gpio.h>
 
-#define BX50V3_BOOTARGS_EXTRA
-#if defined(CONFIG_TARGET_GE_B450V3)
-#define CONFIG_BOARD_NAME	"General Electric B450v3"
-#elif defined(CONFIG_TARGET_GE_B650V3)
-#define CONFIG_BOARD_NAME	"General Electric B650v3"
-#elif defined(CONFIG_TARGET_GE_B850V3)
-#define CONFIG_BOARD_NAME	"General Electric B850v3"
-#undef BX50V3_BOOTARGS_EXTRA
-#define BX50V3_BOOTARGS_EXTRA	"video=DP-1:1024x768@60 " \
-				"video=HDMI-A-1:1024x768@60 "
-#else
-#define CONFIG_BOARD_NAME	"General Electric BA16 Generic"
-#endif
+#define CONFIG_BOARD_NAME	"General Electric Bx50v3"
 
 #define CONFIG_MXC_UART_BASE	UART3_BASE
 #define CONSOLE_DEV	"ttymxc2"
@@ -62,7 +50,6 @@
 /* MMC Configs */
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_BOUNCE_BUFFER
 
 /* USB Configs */
 #ifdef CONFIG_USB
@@ -113,7 +100,7 @@
 		"ro rootwait cma=128M " \
 		"bootcause=${bootcause} " \
 		"${quiet} console=${console} ${rtc_status} " \
-		BX50V3_BOOTARGS_EXTRA "\0" \
+		"${videoargs}" "\0" \
 	"doquiet=" \
 		"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
 			"then setenv quiet; fi\0" \

include/configs/imx6dl-mamoj.h

@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * Configuration settings for the BTicion i.MX6DL Mamoj board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX6DL_MAMOJ_CONFIG_H
+#define __IMX6DL_MAMOJ_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE			SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+#  define CONFIG_ENV_OFFSET		0x100000
+# endif
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"scriptaddr=0x14000000\0"	\
+	"fdt_addr_r=0x13000000\0"	\
+	"kernel_addr_r=0x10008000\0"	\
+	"fdt_high=0xffffffff\0"		\
+	"dfu_alt_info_spl=spl raw 0x2 0x400\0" \
+	"dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART_BASE		UART3_BASE
+
+/* MMC */
+#define CONFIG_SYS_MMC_ENV_DEV		2
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* Ethernet */
+#define CONFIG_FEC_MXC_PHYADDR		1
+#define CONFIG_MII
+
+/* USB */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC			(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS			0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
+
+/* Falcon */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x13000000
+#define CONFIG_CMD_SPL_WRITE_SIZE	(128 * SZ_1K)
+
+/* MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR		0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS		(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR		0x1000  /* 2MB */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SPL */
+#include "imx6_spl.h"
+
+#endif /* __IMX6DL_MAMOJ_CONFIG_H */

include/configs/kp_imx53.h

@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H_
+#define __CONFIG_H_
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/* Eth Configs */
+#define CONFIG_MII
+
+/* USB Configs */
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc1,115200\0"	\
+	"fdt_addr=0x75000000\0"		\
+	"fdt_high=0xffffffff\0"		\
+	"scriptaddr=0x74000000\0"	\
+	"kernel_file=fitImage\0"\
+	"rdinit=/sbin/init\0" \
+	"addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
+	"upd_image=st.4k\0" \
+	"uboot_file=u-boot.imx\0" \
+	"updargs=setenv bootargs console=${console} ${smp}"\
+	       "rdinit=${rdinit} ${debug} ${displayargs}\0" \
+	"loadusb=usb start; " \
+	       "fatload usb 0 ${loadaddr} ${upd_image}\0" \
+	"up=if tftp ${loadaddr} ${uboot_file}; then " \
+	       "setexpr blkc ${filesize} / 0x200; " \
+	       "setexpr blkc ${blkc} + 1; " \
+	       "mmc write ${loadaddr} 0x2 ${blkc}" \
+	"; fi\0"	  \
+	"upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\
+	       "if tftp ${loadaddr} ${wic_file}; then " \
+	       "setexpr blkc ${filesize} / 0x200; " \
+	       "setexpr blkc ${blkc} + 1; " \
+	       "mmc write ${loadaddr} 0x0 ${blkc}" \
+	"; fi\0"	  \
+	"usbupd=echo Booting update from usb ...; " \
+	       "setenv bootargs; " \
+	       "run updargs; " \
+	       "run loadusb; " \
+	       "bootm ${loadaddr}#${fit_config}\0" \
+	BOOTENV
+
+#define CONFIG_BOOTCOMMAND		"run usbupd; run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(512 * SZ_1M)
+#define PHYS_SDRAM_SIZE		(PHYS_SDRAM_1_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_OFFSET      (SZ_1M)
+#define CONFIG_ENV_SIZE        (SZ_8K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif				/* __CONFIG_H_ */

include/configs/kp_imx6q_tpc.h

@@ -21,8 +21,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 
-#define CONFIG_BOUNCE_BUFFER
-
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(4 * SZ_1M)
 

include/configs/mx31pdk.h

@@ -16,8 +16,6 @@
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */
-#define CONFIG_MX31			/* This is a mx31 */
-
 #define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG

include/configs/mx53ppd.h

@@ -198,7 +198,6 @@
 /* FLASH and environment organization */
 #define CONFIG_ENV_OFFSET      (12 * 64 * 1024)
 #define CONFIG_ENV_SIZE        (10 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 
 #define CONFIG_CMD_FUSE

include/configs/mx6_common.h

@@ -15,7 +15,6 @@
 #define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
 #endif
 
-#define CONFIG_MP
 #endif
 #define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_MXC_GPT_HCLK
@@ -51,8 +50,6 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
-/* Filesystems and image support */
-
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_CBSIZE	512
 #define CONFIG_SYS_MAXARGS	32

include/configs/mx7_common.h

@@ -36,9 +36,6 @@
 #define CONFIG_SYS_CBSIZE		512
 #define CONFIG_SYS_MAXARGS		32
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-#endif
-
 /* UART */
 #define CONFIG_MXC_UART
 

include/configs/nitrogen6x.h

@@ -79,161 +79,68 @@
 
 #define CONFIG_PREBOOT                 ""
 
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_DRIVE_SATA "sata "
+#ifdef CONFIG_CMD_MMC
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
 #else
-#define CONFIG_DRIVE_SATA
+#define DISTRO_BOOT_DEV_MMC(func)
 #endif
 
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_DRIVE_MMC "mmc "
+#ifdef CONFIG_CMD_SATA
+#define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0)
 #else
-#define CONFIG_DRIVE_MMC
+#define DISTRO_BOOT_DEV_SATA(func)
 #endif
 
 #ifdef CONFIG_USB_STORAGE
-#define CONFIG_DRIVE_USB "usb "
+#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
 #else
-#define CONFIG_DRIVE_USB
+#define DISTRO_BOOT_DEV_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_PXE
+#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
+#else
+#define DISTRO_BOOT_DEV_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define DISTRO_BOOT_DEV_DHCP(func)
 #endif
 
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB
-#define CONFIG_UMSDEVS CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
 
 #if defined(CONFIG_SABRELITE)
+#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
+#else
+/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */
+#define FDTFILE
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	DISTRO_BOOT_DEV_MMC(func) \
+	DISTRO_BOOT_DEV_SATA(func) \
+	DISTRO_BOOT_DEV_USB(func) \
+	DISTRO_BOOT_DEV_PXE(func) \
+	DISTRO_BOOT_DEV_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"script=boot.scr\0" \
-	"uimage=uImage\0" \
 	"console=ttymxc1\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_file=imx6q-sabrelite.dtb\0" \
-	"fdt_addr=0x18000000\0" \
-	"boot_fdt=try\0" \
+	"fdt_addr_r=0x18000000\0" \
+	FDTFILE \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0"  \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
 	"ip_dyn=yes\0" \
 	"usb_pgood_delay=2000\0" \
-	"mmcdevs=0 1\0" \
-	"mmcpart=1\0" \
-	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=${mmcroot}\0" \
-	"loadbootscript=" \
-		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loaduimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootm; " \
-		"fi;\0" \
-	"netargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/nfs " \
-	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-		"netboot=echo Booting from net ...; " \
-		"run netargs; " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${uimage}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootm ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootm; " \
-				"else " \
-					"echo WARN: Cannot load the DT; " \
-				"fi; " \
-			"fi; " \
-		"else " \
-			"bootm; " \
-		"fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-	"for mmcdev in ${mmcdevs}; do " \
-		"mmc dev ${mmcdev}; " \
-		"if mmc rescan; then " \
-			"if run loadbootscript; then " \
-				"run bootscript; " \
-			"else " \
-				"if run loaduimage; then " \
-					"run mmcboot; " \
-				"fi; " \
-			"fi; " \
-		"fi; " \
-	"done; " \
-	"run netboot; "
-#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"bootdevs=" CONFIG_DRIVE_TYPES "\0" \
-	"umsdevs=" CONFIG_UMSDEVS "\0" \
-	"usb_pgood_delay=2000\0" \
-	"console=ttymxc1\0" \
-	"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
-		"sf erase 0xc0000 0x2000 && " \
-		"echo restored environment to factory default ; fi\0" \
-	"bootcmd=for dtype in ${bootdevs}" \
-		"; do " \
-			"if itest.s \"xusb\" == \"x${dtype}\" ; then " \
-				"usb start ;" \
-			"fi; " \
-			"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
-				"load " \
-					"${dtype} ${disk}:1 " \
-					"10008000 " \
-					"/6x_bootscript" \
-					"&& source 10008000 ; " \
-			"done ; " \
-		"done; " \
-		"setenv stdout serial,vga ; " \
-		"echo ; echo 6x_bootscript not found ; " \
-		"echo ; echo serial console at 115200, 8N1 ; echo ; " \
-		"echo details at http://boundarydevices.com/6q_bootscript ; " \
-		"setenv stdout serial;" \
-		"setenv stdin serial,usbkbd;" \
-		"for dtype in ${umsdevs} ; do " \
-			"if itest.s sata == ${dtype}; then " \
-				"initcmd='sata init' ;" \
-			"else " \
-				"initcmd='mmc rescan' ;" \
-			"fi; " \
-			"for disk in 0 1 ; do " \
-				"if $initcmd && $dtype dev $disk ; then " \
-					"setenv stdout serial,vga; " \
-					"echo expose ${dtype} ${disk} " \
-						"over USB; " \
-					"ums 0 $dtype $disk ;" \
-				"fi; " \
-		"	done; " \
-		"done ;" \
-		"setenv stdout serial,vga; " \
-		"echo no block devices found;" \
-		"\0" \
-	"initrd_high=0xffffffff\0" \
-	"upgradeu=for dtype in ${bootdevs}" \
-		"; do " \
-		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
-			"load ${dtype} ${disk}:1 10008000 " \
-				"/6x_upgrade " \
-				"&& source 10008000 ; " \
-		"done ; " \
-	"done\0" \
+	BOOTENV
 
-#endif
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_MEMTEST_START       0x10000000
 #define CONFIG_SYS_MEMTEST_END	       0x10010000

include/fsl_pmic.h

@@ -107,6 +107,7 @@ enum {
 
 /* MC34708 Definitions */
 #define SWx_VOLT_MASK_MC34708	0x3F
+#define SWx_1_110V_MC34708	0x24
 #define SWx_1_250V_MC34708	0x30
 #define SWx_1_300V_MC34708	0x34
 #define TIMER_MASK_MC34708	0x300
@@ -116,4 +117,44 @@ enum {
 #define SWBST_CTRL		31
 #define SWBST_AUTO		0x8
 
+#define MC34708_REG_SW12_OPMODE	28
+
+#define MC34708_SW1AMODE_MASK	0x00000f
+#define MC34708_SW1AMHMODE	0x000010
+#define MC34708_SW1AUOMODE	0x000020
+#define MC34708_SW1DVSSPEED	0x0000c0
+#define MC34708_SW2MODE_MASK	0x03c000
+#define MC34708_SW2MHMODE	0x040000
+#define MC34708_SW2UOMODE	0x080000
+#define MC34708_SW2DVSSPEED	0x300000
+#define MC34708_PLLEN		0x400000
+#define MC34708_PLLX		0x800000
+
+#define MC34708_REG_SW345_OPMODE	29
+
+#define MC34708_SW3MODE_MASK	0x00000f
+#define MC34708_SW3MHMODE	0x000010
+#define MC34708_SW3UOMODE	0x000020
+#define MC34708_SW4AMODE_MASK	0x0003c0
+#define MC34708_SW4AMHMODE	0x000400
+#define MC34708_SW4AUOMODE	0x000800
+#define MC34708_SW4BMODE_MASK	0x00f000
+#define MC34708_SW4BMHMODE	0x010000
+#define MC34708_SW4BUOMODE	0x020000
+#define MC34708_SW5MODE_MASK	0x3c0000
+#define MC34708_SW5MHMODE	0x400000
+#define MC34708_SW5UOMODE	0x800000
+
+#define SW_MODE_OFFOFF		0x00
+#define SW_MODE_PWMOFF		0x01
+#define SW_MODE_PFMOFF		0x03
+#define SW_MODE_APSOFF		0x04
+#define SW_MODE_PWMPWM		0x05
+#define SW_MODE_PWMAPS		0x06
+#define SW_MODE_APSAPS		0x08
+#define SW_MODE_APSPFM		0x0c
+#define SW_MODE_PWMPFM		0x0d
+#define SW_MODE_PFMPFM		0x0f
+
+#define MC34708_TRANSFER_SIZE 3
 #endif

include/power/pmic.h

@@ -297,6 +297,15 @@ int pmic_reg_write(struct udevice *dev, uint reg, uint value);
  */
 int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);
 
+/*
+ * This structure holds the private data for PMIC uclass
+ * For now we store information about the number of bytes
+ * being sent at once to the device.
+ */
+struct uc_pmic_priv {
+	uint trans_len;
+};
+
 #endif /* CONFIG_DM_PMIC */
 
 #ifdef CONFIG_POWER

test/dm/pmic.c

@@ -19,11 +19,12 @@
 #include <power/pmic.h>
 #include <power/sandbox_pmic.h>
 #include <test/ut.h>
+#include <fsl_pmic.h>
 
 /* Test PMIC get method */
-static int dm_test_power_pmic_get(struct unit_test_state *uts)
+
+static inline int power_pmic_get(struct unit_test_state *uts, char *name)
 {
-	const char *name = "sandbox_pmic";
 	struct udevice *dev;
 
 	ut_assertok(pmic_get(name, &dev));
@@ -34,8 +35,26 @@ static int dm_test_power_pmic_get(struct unit_test_state *uts)
 
 	return 0;
 }
+
+/* Test PMIC get method */
+static int dm_test_power_pmic_get(struct unit_test_state *uts)
+{
+	power_pmic_get(uts, "sandbox_pmic");
+
+	return 0;
+}
 DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT);
 
+/* PMIC get method - MC34708 - for 3 bytes transmission */
+static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
+{
+	power_pmic_get(uts, "pmic@41");
+
+	return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_get, DM_TESTF_SCAN_FDT);
+
 /* Test PMIC I/O */
 static int dm_test_power_pmic_io(struct unit_test_state *uts)
 {
@@ -64,3 +83,48 @@ static int dm_test_power_pmic_io(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT);
+
+#define MC34708_PMIC_REG_COUNT 64
+#define MC34708_PMIC_TEST_VAL 0x125534
+static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	int reg_count;
+
+	ut_assertok(pmic_get("pmic@41", &dev));
+
+	/* Check number of PMIC registers */
+	reg_count = pmic_reg_count(dev);
+	ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
+
+	return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_regs_check, DM_TESTF_SCAN_FDT);
+
+static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	int val;
+
+	ut_assertok(pmic_get("pmic@41", &dev));
+
+	/* Check if single 3 byte read is successful */
+	val = pmic_reg_read(dev, REG_POWER_CTL2);
+	ut_asserteq(val, 0x422100);
+
+	/* Check if RW works */
+	val = 0;
+	ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
+	ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
+	val = pmic_reg_read(dev, REG_RTC_TIME);
+	ut_asserteq(val, MC34708_PMIC_TEST_VAL);
+
+	pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
+	val = pmic_reg_read(dev, REG_POWER_CTL2);
+	ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
+
+	return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_rw_val, DM_TESTF_SCAN_FDT);