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@@ -26,12 +26,12 @@
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PORT_GP_18(0, fn, sfx), \
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PORT_GP_23(1, fn, sfx), \
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PORT_GP_26(2, fn, sfx), \
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- PORT_GP_12(3, fn, sfx), \
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+ PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_1(3, 12, fn, sfx), \
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PORT_GP_1(3, 13, fn, sfx), \
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PORT_GP_1(3, 14, fn, sfx), \
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PORT_GP_1(3, 15, fn, sfx), \
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- PORT_GP_11(4, fn, sfx), \
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+ PORT_GP_CFG_11(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_20(5, fn, sfx), \
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PORT_GP_18(6, fn, sfx)
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/*
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@@ -5151,8 +5151,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ },
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};
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+enum ioctrl_regs {
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+ POCCTRL,
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+};
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+
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+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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+ [POCCTRL] = { 0xe6060380, },
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+ { /* sentinel */ },
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+};
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+
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+static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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+{
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+ int bit = -EINVAL;
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+
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+ *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
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+
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+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
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+ bit = pin & 0x1f;
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+
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+ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
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+ bit = (pin & 0x1f) + 19;
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+
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+ return bit;
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+}
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+
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+static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
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+ .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
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+};
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+
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const struct sh_pfc_soc_info r8a77990_pinmux_info = {
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.name = "r8a77990_pfc",
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+ .ops = &r8a77990_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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@@ -5165,6 +5194,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = {
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.nr_functions = ARRAY_SIZE(pinmux_functions),
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.cfg_regs = pinmux_config_regs,
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+ .ioctrl_regs = pinmux_ioctrl_regs,
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.pinmux_data = pinmux_data,
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.pinmux_data_size = ARRAY_SIZE(pinmux_data),
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