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@@ -57,6 +57,16 @@ static void at91sam9261ek_nand_hw_init(void)
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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/* Configure SMC CS3 for NAND/SmartMedia */
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+#ifdef CONFIG_AT91SAM9G10EK
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+ at91_sys_write(AT91_SMC_SETUP(3),
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+ AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
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+ AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
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+ at91_sys_write(AT91_SMC_PULSE(3),
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+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) |
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+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7));
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+ at91_sys_write(AT91_SMC_CYCLE(3),
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+ AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
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+#else
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at91_sys_write(AT91_SMC_SETUP(3),
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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@@ -65,6 +75,7 @@ static void at91sam9261ek_nand_hw_init(void)
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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+#endif
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at91_sys_write(AT91_SMC_MODE(3),
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_EXNWMODE_DISABLE |
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@@ -92,6 +103,21 @@ static void at91sam9261ek_nand_hw_init(void)
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static void at91sam9261ek_dm9000_hw_init(void)
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static void at91sam9261ek_dm9000_hw_init(void)
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{
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{
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/* Configure SMC CS2 for DM9000 */
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/* Configure SMC CS2 for DM9000 */
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+#ifdef CONFIG_AT91SAM9G10EK
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+ at91_sys_write(AT91_SMC_SETUP(2),
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+ AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) |
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+ AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0));
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+ at91_sys_write(AT91_SMC_PULSE(2),
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+ AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) |
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+ AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8));
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+ at91_sys_write(AT91_SMC_CYCLE(2),
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+ AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20));
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+ at91_sys_write(AT91_SMC_MODE(2),
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+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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+ AT91_SMC_EXNWMODE_DISABLE |
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+ AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
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+ AT91_SMC_TDF_(1));
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+#else
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at91_sys_write(AT91_SMC_SETUP(2),
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at91_sys_write(AT91_SMC_SETUP(2),
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AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
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AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
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@@ -105,6 +131,7 @@ static void at91sam9261ek_dm9000_hw_init(void)
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
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AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
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AT91_SMC_TDF_(1));
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AT91_SMC_TDF_(1));
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+#endif
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/* Configure Reset signal as output */
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/* Configure Reset signal as output */
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at91_set_gpio_output(AT91_PIN_PC10, 0);
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at91_set_gpio_output(AT91_PIN_PC10, 0);
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@@ -169,7 +196,11 @@ static void at91sam9261ek_lcd_hw_init(void)
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at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
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at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
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+#ifdef CONFIG_AT91SAM9G10EK
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+ gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE;
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+#else
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gd->fb_base = AT91SAM9261_SRAM_BASE;
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gd->fb_base = AT91SAM9261_SRAM_BASE;
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+#endif
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}
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}
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#ifdef CONFIG_LCD_INFO
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#ifdef CONFIG_LCD_INFO
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@@ -207,8 +238,13 @@ int board_init(void)
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/* Enable Ctrlc */
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/* Enable Ctrlc */
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console_init_f();
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console_init_f();
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+#ifdef CONFIG_AT91SAM9G10EK
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+ /* arch number of AT91SAM9G10EK-Board */
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+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
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+#else
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/* arch number of AT91SAM9261EK-Board */
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/* arch number of AT91SAM9261EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
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+#endif
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/* adress of boot parameters */
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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