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x86: qemu: add a cpu uclass driver for qemu target

Add a cpu uclass driver for qemu. Previously, the qemu target gets cpu
number from board dts files, which are manually created at compile time.
This does not scale when more cpus are assigned to guest as the dts files
must be modified as well.

This patch adds a cpu uclass driver for qemu targets to directly read
online cpu number from firmware.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan 9 жил өмнө
parent
commit
5a694056fe

+ 1 - 1
arch/x86/cpu/qemu/Makefile

@@ -7,5 +7,5 @@
 ifndef CONFIG_EFI_STUB
 ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 obj-y += car.o dram.o
 endif
 endif
-obj-y += fw_cfg.o qemu.o
+obj-y += cpu.o fw_cfg.o qemu.o
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o

+ 57 - 0
arch/x86/cpu/qemu/cpu.c

@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2015, Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu.h>
+#include <asm/fw_cfg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cpu_qemu_bind(struct udevice *dev)
+{
+	struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+	plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				      "intel,apic-id", -1);
+
+	return 0;
+}
+
+int cpu_qemu_get_desc(struct udevice *dev, char *buf, int size)
+{
+	if (size < CPU_MAX_NAME_LEN)
+		return -ENOSPC;
+
+	cpu_get_name(buf);
+
+	return 0;
+}
+
+static int cpu_qemu_get_count(struct udevice *dev)
+{
+	return qemu_fwcfg_online_cpus();
+}
+
+static const struct cpu_ops cpu_qemu_ops = {
+	.get_desc	= cpu_qemu_get_desc,
+	.get_count	= cpu_qemu_get_count,
+};
+
+static const struct udevice_id cpu_qemu_ids[] = {
+	{ .compatible = "cpu-qemu" },
+	{ }
+};
+
+U_BOOT_DRIVER(cpu_qemu_drv) = {
+	.name		= "cpu_qemu",
+	.id		= UCLASS_CPU,
+	.of_match	= cpu_qemu_ids,
+	.bind		= cpu_qemu_bind,
+	.ops		= &cpu_qemu_ops,
+};

+ 2 - 2
arch/x86/dts/qemu-x86_i440fx.dts

@@ -32,14 +32,14 @@
 
 
 		cpu@0 {
 		cpu@0 {
 			device_type = "cpu";
 			device_type = "cpu";
-			compatible = "cpu-x86";
+			compatible = "cpu-qemu";
 			reg = <0>;
 			reg = <0>;
 			intel,apic-id = <0>;
 			intel,apic-id = <0>;
 		};
 		};
 
 
 		cpu@1 {
 		cpu@1 {
 			device_type = "cpu";
 			device_type = "cpu";
-			compatible = "cpu-x86";
+			compatible = "cpu-qemu";
 			reg = <1>;
 			reg = <1>;
 			intel,apic-id = <1>;
 			intel,apic-id = <1>;
 		};
 		};

+ 2 - 2
arch/x86/dts/qemu-x86_q35.dts

@@ -43,14 +43,14 @@
 
 
 		cpu@0 {
 		cpu@0 {
 			device_type = "cpu";
 			device_type = "cpu";
-			compatible = "cpu-x86";
+			compatible = "cpu-qemu";
 			reg = <0>;
 			reg = <0>;
 			intel,apic-id = <0>;
 			intel,apic-id = <0>;
 		};
 		};
 
 
 		cpu@1 {
 		cpu@1 {
 			device_type = "cpu";
 			device_type = "cpu";
-			compatible = "cpu-x86";
+			compatible = "cpu-qemu";
 			reg = <1>;
 			reg = <1>;
 			intel,apic-id = <1>;
 			intel,apic-id = <1>;
 		};
 		};