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@@ -11,6 +11,11 @@
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* System Programming
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*/
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+/*
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+ * Note that any console output (e.g. debug()) in this file will likely fail
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+ * since the MTRR registers are sometimes in flux.
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+ */
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+
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#include <common.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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@@ -19,27 +24,29 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* Prepare to adjust MTRRs */
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-void mtrr_open(struct mtrr_state *state)
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+void mtrr_open(struct mtrr_state *state, bool do_caches)
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{
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if (!gd->arch.has_mtrr)
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return;
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- state->enable_cache = dcache_status();
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+ if (do_caches) {
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+ state->enable_cache = dcache_status();
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- if (state->enable_cache)
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- disable_caches();
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+ if (state->enable_cache)
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+ disable_caches();
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+ }
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state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
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wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
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}
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/* Clean up after adjusting MTRRs, and enable them */
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-void mtrr_close(struct mtrr_state *state)
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+void mtrr_close(struct mtrr_state *state, bool do_caches)
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{
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if (!gd->arch.has_mtrr)
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return;
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wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
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- if (state->enable_cache)
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+ if (do_caches && state->enable_cache)
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enable_caches();
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}
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@@ -50,10 +57,14 @@ int mtrr_commit(bool do_caches)
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uint64_t mask;
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int i;
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+ debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
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+ gd->arch.mtrr_req_count);
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if (!gd->arch.has_mtrr)
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return -ENOSYS;
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- mtrr_open(&state);
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+ debug("open\n");
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+ mtrr_open(&state, do_caches);
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+ debug("open done\n");
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for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) {
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mask = ~(req->size - 1);
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mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
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@@ -62,9 +73,12 @@ int mtrr_commit(bool do_caches)
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}
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/* Clear the ones that are unused */
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+ debug("clear\n");
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for (; i < MTRR_COUNT; i++)
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wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
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- mtrr_close(&state);
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+ debug("close\n");
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+ mtrr_close(&state, do_caches);
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+ debug("mtrr done\n");
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return 0;
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}
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@@ -74,6 +88,7 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size)
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struct mtrr_request *req;
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uint64_t mask;
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+ debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
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if (!gd->arch.has_mtrr)
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return -ENOSYS;
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