arm: am33xx: Fix MPU opp selection

Update MPU frequencies and voltages as per the latest
DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4.
Below is the consolidated data:

MPU values for PG 2.0 and later(Package ZCZ and ZCE):

 -------------------------------------------------------
|	|	  ZCZ		|	  ZCE		|
|-------------------------------------------------------|
|	| VDD[V]   | ARM [MHz]	| VDD[V]   | ARM [MHz]  |
|-------|----------|------------|----------|------------|
| NITRO |  1.325   |   1000     |   NA     |    NA      |
|-------|----------|------------|----------|------------|
| TURBO |   1.26   |    800	|   NA     |    NA      |
|-------|----------|------------|----------|------------|
|OPP120 |   1.20   |    720     |   NA     |    NA      |
|-------|----------|------------|----------|------------|
|OPP100 |   1.10   |    600     |   1.10   |    600     |
|-------|----------|------------|----------|------------|
| OPP50 |   0.95   |    300     |   0.95   |    300     |
 -------------------------------------------------------

There is no eFuse blown on PG1.0 Silicons due to which there is
no way to detect the maximum frequencies supported. So default
to OPP100 for which both frequency and voltages are common on both
the packages.

[1] http://www.ti.com/lit/ds/symlink/am3356.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

arch/arm/include/asm/arch-am33xx/clocks_am33xx.h

@@ -16,7 +16,7 @@
 #define MPUPLL_M_800	800
 #define MPUPLL_M_720	720
 #define MPUPLL_M_600	600
-#define MPUPLL_M_550	550
+#define MPUPLL_M_500	500
 #define MPUPLL_M_300	300
 
 #define UART_RESET		(0x1 << 1)

arch/arm/include/asm/arch-am33xx/cpu.h

@@ -49,6 +49,14 @@
 #define TI81XX				0xB81E
 #define DEVICE_ID			(CTRL_BASE + 0x0600)
 #define DEVICE_ID_MASK			0x1FFF
+#define PACKAGE_TYPE_SHIFT		16
+#define PACKAGE_TYPE_MASK		(3 << 16)
+
+/* Package Type */
+#define PACKAGE_TYPE_UNDEFINED		0x0
+#define PACKAGE_TYPE_ZCZ		0x1
+#define PACKAGE_TYPE_ZCE		0x2
+#define PACKAGE_TYPE_RESERVED		0x3
 
 /* MPU max frequencies */
 #define AM335X_ZCZ_300			0x1FEF

arch/arm/mach-omap2/Kconfig

@@ -150,7 +150,7 @@ endchoice
 
 config SYS_MPUCLK
 	int "MPU CLK speed"
-	default 550
+	default 500
 	help
 	  Defines the MPU clock speed (in MHz).
 

arch/arm/mach-omap2/am33xx/sys_info.c

@@ -132,13 +132,21 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 
 	sil_rev = readl(&cdev->deviceid) >> 28;
 
-	if (sil_rev == 1)
-		/* PG 2.0, efuse may not be set. */
-		return MPUPLL_M_800;
-	else if (sil_rev >= 2) {
+	if (sil_rev == 0) {
+		/* No efuse in PG 1.0. Use max speed */
+		return MPUPLL_M_720;
+	} else if (sil_rev >= 1) {
 		/* Check what the efuse says our max speed is. */
-		int efuse_arm_mpu_max_freq;
+		int efuse_arm_mpu_max_freq, package_type;
 		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+		package_type = (efuse_arm_mpu_max_freq & PACKAGE_TYPE_MASK) >>
+				PACKAGE_TYPE_SHIFT;
+
+		/* PG 2.0, efuse may not be set. */
+		if (package_type == PACKAGE_TYPE_UNDEFINED || package_type ==
+		    PACKAGE_TYPE_RESERVED)
+			return MPUPLL_M_800;
+
 		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
 		case AM335X_ZCZ_1000:
 			return MPUPLL_M_1000;
@@ -155,14 +163,14 @@ int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
 		}
 	}
 
-	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
+	/* unknown, use the PG1.0 max */
 	return MPUPLL_M_720;
 }
 
 int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
 {
-	/* For PG2.1 and later, we have one set of values. */
-	if (sil_rev >= 2) {
+	/* For PG2.0 and later, we have one set of values. */
+	if (sil_rev >= 1) {
 		switch (frequency) {
 		case MPUPLL_M_1000:
 			return TPS65910_OP_REG_SEL_1_3_2_5;
@@ -171,12 +179,13 @@ int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
 		case MPUPLL_M_720:
 			return TPS65910_OP_REG_SEL_1_2_0;
 		case MPUPLL_M_600:
+		case MPUPLL_M_500:
 		case MPUPLL_M_300:
-			return TPS65910_OP_REG_SEL_1_1_3;
+			return TPS65910_OP_REG_SEL_1_1_0;
 		}
 	}
 
-	/* Default to PG1.0/PG2.0 values. */
-	return TPS65910_OP_REG_SEL_1_1_3;
+	/* Default to PG1.0 values. */
+	return TPS65910_OP_REG_SEL_1_2_6;
 }
 #endif

include/power/tps65910.h

@@ -62,6 +62,7 @@ enum {
 
 #define TPS65910_OP_REG_SEL_MASK			(0x7F)
 #define TPS65910_OP_REG_SEL_0_9_5			(0x1F)	/* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_0			(0x2B)	/* 1.1000 V */
 #define TPS65910_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
 #define TPS65910_OP_REG_SEL_1_2_0			(0x33)	/* 1.2000 V */
 #define TPS65910_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */