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@@ -0,0 +1,32 @@
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+#include <common.h>
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+#include <netdev.h>
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+#include <miiphy.h>
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+#include <asm/gpio.h>
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+#include <asm/io.h>
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+#include <asm/arch/clock.h>
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+#include <asm/arch/gpio.h>
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+
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+int sunxi_gmac_initialize(bd_t *bis)
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+{
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+ int pin;
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+ struct sunxi_ccm_reg *const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+
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+ /* Set up clock gating */
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+ setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
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+
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+ /* Set MII clock */
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+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
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+ CCM_GMAC_CTRL_GPIT_RGMII);
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+
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+ /* Configure pin mux settings for GMAC */
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+ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
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+ /* skip unused pins in RGMII mode */
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+ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
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+ continue;
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+ sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
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+ sunxi_gpio_set_drv(pin, 3);
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+ }
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+
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+ return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
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+}
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