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@@ -381,7 +381,7 @@ int last_stage_init(void)
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ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
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}
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- /* wait for FPGA done */
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+ /* wait for FPGA done; then reset FPGA */
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for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
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unsigned int ctr = 0;
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@@ -396,6 +396,12 @@ int last_stage_init(void)
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break;
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}
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}
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+
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+ pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
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+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
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+ udelay(10);
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+ pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
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+ MCFPGA_RESET_N);
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}
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if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
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