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@@ -0,0 +1,389 @@
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+/*
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+ * Allwinner DW HDMI bridge
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+ *
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+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <display.h>
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+#include <dm.h>
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+#include <dw_hdmi.h>
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+#include <edid.h>
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+#include <asm/io.h>
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+#include <asm/arch/clock.h>
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+#include <asm/arch/lcdc.h>
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+
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+struct sunxi_dw_hdmi_priv {
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+ struct dw_hdmi hdmi;
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+ int mux;
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+};
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+
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+struct sunxi_hdmi_phy {
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+ u32 pol;
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+ u32 res1[3];
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+ u32 read_en;
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+ u32 unscramble;
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+ u32 res2[2];
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+ u32 ctrl;
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+ u32 unk1;
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+ u32 unk2;
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+ u32 pll;
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+ u32 clk;
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+ u32 unk3;
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+ u32 status;
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+};
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+
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+#define HDMI_PHY_OFFS 0x10000
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+
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+static int sunxi_dw_hdmi_get_divider(uint clock)
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+{
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+ /*
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+ * Due to missing documentaion of HDMI PHY, we know correct
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+ * settings only for following four PHY dividers. Select one
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+ * based on clock speed.
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+ */
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+ if (clock <= 27000000)
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+ return 11;
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+ else if (clock <= 74250000)
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+ return 4;
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+ else if (clock <= 148500000)
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+ return 2;
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+ else
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+ return 1;
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+}
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+
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+static void sunxi_dw_hdmi_phy_init(void)
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+{
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+ struct sunxi_hdmi_phy * const phy =
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+ (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
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+ unsigned long tmo;
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+ u32 tmp;
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+
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+ /*
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+ * HDMI PHY settings are taken as-is from Allwinner BSP code.
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+ * There is no documentation.
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+ */
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+ writel(0, &phy->ctrl);
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+ setbits_le32(&phy->ctrl, BIT(0));
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+ udelay(5);
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+ setbits_le32(&phy->ctrl, BIT(16));
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+ setbits_le32(&phy->ctrl, BIT(1));
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+ udelay(10);
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+ setbits_le32(&phy->ctrl, BIT(2));
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+ udelay(5);
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+ setbits_le32(&phy->ctrl, BIT(3));
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+ udelay(40);
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+ setbits_le32(&phy->ctrl, BIT(19));
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+ udelay(100);
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+ setbits_le32(&phy->ctrl, BIT(18));
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+ setbits_le32(&phy->ctrl, 7 << 4);
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+
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+ /* Note that Allwinner code doesn't fail in case of timeout */
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+ tmo = timer_get_us() + 2000;
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+ while ((readl(&phy->status) & 0x80) == 0) {
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+ if (timer_get_us() > tmo) {
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+ printf("Warning: HDMI PHY init timeout!\n");
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+ break;
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+ }
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+ }
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+
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+ setbits_le32(&phy->ctrl, 0xf << 8);
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+ setbits_le32(&phy->ctrl, BIT(7));
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+
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+ writel(0x39dc5040, &phy->pll);
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+ writel(0x80084343, &phy->clk);
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+ udelay(10000);
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+ writel(1, &phy->unk3);
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+ setbits_le32(&phy->pll, BIT(25));
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+ udelay(100000);
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+ tmp = (readl(&phy->status) & 0x1f800) >> 11;
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+ setbits_le32(&phy->pll, BIT(31) | BIT(30));
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+ setbits_le32(&phy->pll, tmp);
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+ writel(0x01FF0F7F, &phy->ctrl);
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+ writel(0x80639000, &phy->unk1);
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+ writel(0x0F81C405, &phy->unk2);
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+
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+ /* enable read access to HDMI controller */
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+ writel(0x54524545, &phy->read_en);
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+ /* descramble register offsets */
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+ writel(0x42494E47, &phy->unscramble);
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+}
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+
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+static int sunxi_dw_hdmi_get_plug_in_status(void)
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+{
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+ struct sunxi_hdmi_phy * const phy =
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+ (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
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+
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+ return !!(readl(&phy->status) & (1 << 19));
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+}
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+
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+static int sunxi_dw_hdmi_wait_for_hpd(void)
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+{
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+ ulong start;
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+
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+ start = get_timer(0);
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+ do {
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+ if (sunxi_dw_hdmi_get_plug_in_status())
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+ return 0;
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+ udelay(100);
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+ } while (get_timer(start) < 300);
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+
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+ return -1;
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+}
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+
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+static void sunxi_dw_hdmi_phy_set(uint clock)
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+{
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+ struct sunxi_hdmi_phy * const phy =
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+ (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
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+ int div = sunxi_dw_hdmi_get_divider(clock);
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+ u32 tmp;
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+
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+ /*
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+ * Unfortunately, we don't know much about those magic
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+ * numbers. They are taken from Allwinner BSP driver.
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+ */
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+ switch (div) {
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+ case 1:
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+ writel(0x30dc5fc0, &phy->pll);
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+ writel(0x800863C0, &phy->clk);
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+ mdelay(10);
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+ writel(0x00000001, &phy->unk3);
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+ setbits_le32(&phy->pll, BIT(25));
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+ mdelay(200);
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+ tmp = (readl(&phy->status) & 0x1f800) >> 11;
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+ setbits_le32(&phy->pll, BIT(31) | BIT(30));
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+ if (tmp < 0x3d)
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+ setbits_le32(&phy->pll, tmp + 2);
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+ else
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+ setbits_le32(&phy->pll, 0x3f);
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+ mdelay(100);
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+ writel(0x01FFFF7F, &phy->ctrl);
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+ writel(0x8063b000, &phy->unk1);
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+ writel(0x0F8246B5, &phy->unk2);
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+ break;
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+ case 2:
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+ writel(0x39dc5040, &phy->pll);
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+ writel(0x80084381, &phy->clk);
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+ mdelay(10);
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+ writel(0x00000001, &phy->unk3);
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+ setbits_le32(&phy->pll, BIT(25));
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+ mdelay(100);
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+ tmp = (readl(&phy->status) & 0x1f800) >> 11;
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+ setbits_le32(&phy->pll, BIT(31) | BIT(30));
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+ setbits_le32(&phy->pll, tmp);
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+ writel(0x01FFFF7F, &phy->ctrl);
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+ writel(0x8063a800, &phy->unk1);
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+ writel(0x0F81C485, &phy->unk2);
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+ break;
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+ case 4:
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+ writel(0x39dc5040, &phy->pll);
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+ writel(0x80084343, &phy->clk);
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+ mdelay(10);
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+ writel(0x00000001, &phy->unk3);
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+ setbits_le32(&phy->pll, BIT(25));
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+ mdelay(100);
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+ tmp = (readl(&phy->status) & 0x1f800) >> 11;
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+ setbits_le32(&phy->pll, BIT(31) | BIT(30));
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+ setbits_le32(&phy->pll, tmp);
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+ writel(0x01FFFF7F, &phy->ctrl);
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+ writel(0x8063b000, &phy->unk1);
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+ writel(0x0F81C405, &phy->unk2);
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+ break;
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+ case 11:
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+ writel(0x39dc5040, &phy->pll);
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+ writel(0x8008430a, &phy->clk);
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+ mdelay(10);
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+ writel(0x00000001, &phy->unk3);
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+ setbits_le32(&phy->pll, BIT(25));
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+ mdelay(100);
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+ tmp = (readl(&phy->status) & 0x1f800) >> 11;
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+ setbits_le32(&phy->pll, BIT(31) | BIT(30));
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+ setbits_le32(&phy->pll, tmp);
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+ writel(0x01FFFF7F, &phy->ctrl);
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+ writel(0x8063b000, &phy->unk1);
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+ writel(0x0F81C405, &phy->unk2);
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+ break;
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+ }
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+}
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+
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+static void sunxi_dw_hdmi_pll_set(uint clk_khz)
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+{
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+ int value, n, m, div = 0, diff;
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+ int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
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+
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+ div = sunxi_dw_hdmi_get_divider(clk_khz * 1000);
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+
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+ /*
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+ * Find the lowest divider resulting in a matching clock. If there
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+ * is no match, pick the closest lower clock, as monitors tend to
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+ * not sync to higher frequencies.
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+ */
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+ for (m = 1; m <= 16; m++) {
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+ n = (m * div * clk_khz) / 24000;
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+
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+ if ((n >= 1) && (n <= 128)) {
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+ value = (24000 * n) / m / div;
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+ diff = clk_khz - value;
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+ if (diff < best_diff) {
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+ best_diff = diff;
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+ best_m = m;
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+ best_n = n;
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+ }
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+ }
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+ }
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+
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+ clock_set_pll3_factors(best_m, best_n);
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+ debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
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+ clk_khz, (clock_get_pll3() / 1000) / div,
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+ best_n, best_m, div);
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+}
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+
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+static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
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+ int bpp)
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+{
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+ struct sunxi_ccm_reg * const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+ int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ);
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+ struct sunxi_lcdc_reg *lcdc;
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+
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+ if (mux == 0) {
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+ lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
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+
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+ /* Reset off */
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+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
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+
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+ /* Clock on */
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+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
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+ writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
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+ &ccm->lcd0_clk_cfg);
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+ } else {
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+ lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
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+
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+ /* Reset off */
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+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
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+
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+ /* Clock on */
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+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
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+ writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
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+ &ccm->lcd1_clk_cfg);
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+ }
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+
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+ lcdc_init(lcdc);
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+ lcdc_tcon1_mode_set(lcdc, edid, false, false);
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+ lcdc_enable(lcdc, bpp);
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+}
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+
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+static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
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+{
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+ sunxi_dw_hdmi_pll_set(mpixelclock/1000);
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+ sunxi_dw_hdmi_phy_set(mpixelclock);
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+
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+ return 0;
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+}
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+
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+static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
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+{
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+ struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
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+
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+ return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
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+}
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+
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+static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
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+ const struct display_timing *edid)
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+{
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+ struct sunxi_hdmi_phy * const phy =
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+ (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
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+ struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
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+ int ret;
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+
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+ ret = dw_hdmi_enable(&priv->hdmi, edid);
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+ if (ret)
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+ return ret;
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+
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+ sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
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+
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+ /*
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+ * Condition in original code is a bit weird. This is attempt
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+ * to make it more reasonable and it works. It could be that
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+ * bits and conditions are related and should be separated.
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+ */
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+ if (!((edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) &&
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+ (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH))) {
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+ setbits_le32(&phy->pol, 0x300);
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+ }
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+
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+ setbits_le32(&phy->ctrl, 0xf << 12);
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+
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+ /*
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+ * This is last hdmi access before boot, so scramble addresses
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+ * again or othwerwise BSP driver won't work. Dummy read is
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+ * needed or otherwise last write doesn't get written correctly.
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+ */
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+ (void)readb(SUNXI_HDMI_BASE);
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+ writel(0, &phy->unscramble);
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+
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+ return 0;
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+}
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+
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+static int sunxi_dw_hdmi_probe(struct udevice *dev)
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+{
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+ struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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+ struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
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+ struct sunxi_ccm_reg * const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+ int ret;
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+
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+ /* Set pll3 to 297 MHz */
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+ clock_set_pll3(297000000);
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+
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+ /* Set hdmi parent to pll3 */
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+ clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
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+ CCM_HDMI_CTRL_PLL3);
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+
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+ /* Set ahb gating to pass */
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+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
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+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
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+ setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
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+ setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
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+
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+ /* Clock on */
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+ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
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+
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+ sunxi_dw_hdmi_phy_init();
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+
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+ ret = sunxi_dw_hdmi_wait_for_hpd();
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+ if (ret < 0) {
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+ debug("hdmi can not get hpd signal\n");
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+ return -1;
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+ }
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+
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+ priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
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+ priv->hdmi.i2c_clk_high = 0xd8;
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+ priv->hdmi.i2c_clk_low = 0xfe;
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+ priv->hdmi.reg_io_width = 1;
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+ priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
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+ priv->mux = uc_plat->source_id;
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+
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+ dw_hdmi_init(&priv->hdmi);
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+
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+ return 0;
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+}
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+
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+static const struct dm_display_ops sunxi_dw_hdmi_ops = {
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+ .read_edid = sunxi_dw_hdmi_read_edid,
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+ .enable = sunxi_dw_hdmi_enable,
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+};
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+
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+U_BOOT_DRIVER(sunxi_dw_hdmi) = {
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|
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+ .name = "sunxi_dw_hdmi",
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|
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+ .id = UCLASS_DISPLAY,
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+ .ops = &sunxi_dw_hdmi_ops,
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|
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+ .probe = sunxi_dw_hdmi_probe,
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|
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+ .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
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|
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+};
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|
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+
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|
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+U_BOOT_DEVICE(sunxi_dw_hdmi) = {
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|
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+ .name = "sunxi_dw_hdmi"
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|
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+};
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Jernej Skrabec