Merge branch 'master' of git://git.denx.de/u-boot-sh

arch/sh/cpu/sh4/cache.c

@@ -91,7 +91,7 @@ int cache_control(unsigned int cmd)
 	return 0;
 }
 
-void dcache_wback_range(u32 start, u32 end)
+void flush_dcache_range(unsigned long start, unsigned long end)
 {
 	u32 v;
 
@@ -102,7 +102,7 @@ void dcache_wback_range(u32 start, u32 end)
 	}
 }
 
-void dcache_invalid_range(u32 start, u32 end)
+void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
 	u32 v;
 

arch/sh/cpu/sh4/cpu.c

@@ -41,7 +41,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 void flush_cache (unsigned long addr, unsigned long size)
 {
-	dcache_invalid_range( addr , addr + size );
+	invalidate_dcache_range(addr , addr + size);
 }
 
 void icache_enable (void)

arch/sh/include/asm/cache.h

@@ -10,9 +10,6 @@ int cache_control(unsigned int cmd);
 struct __large_struct { unsigned long buf[100]; };
 #define __m(x) (*(struct __large_struct *)(x))
 
-void dcache_wback_range(u32 start, u32 end);
-void dcache_invalid_range(u32 start, u32 end);
-
 #else
 
 /*

arch/sh/lib/time.c

@@ -17,15 +17,17 @@
 #include <asm/io.h>
 #include <sh_tmu.h>
 
+#define TCR_TPSC 0x07
+
 static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
 
-static u16 bit;
 static unsigned long last_tcnt;
 static unsigned long long overflow_ticks;
 
 unsigned long get_tbclk(void)
 {
-	return get_tmu0_clk_rate() >> ((bit + 1) * 2);
+	u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
+	return get_tmu0_clk_rate() >> ((tmu_bit + 1) * 2);
 }
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
@@ -60,8 +62,8 @@ static void tmu_timer_stop(unsigned int timer)
 
 int timer_init(void)
 {
-	bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
-	writew(readw(&tmu->tcr0) | bit, &tmu->tcr0);
+	u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
+	writew((readw(&tmu->tcr0) & ~TCR_TPSC) | tmu_bit, &tmu->tcr0);
 
 	tmu_timer_stop(0);
 	tmu_timer_start(0);

drivers/serial/serial_sh.c

@@ -1,5 +1,6 @@
 /*
  * SuperH SCIF device driver.
+ * Copyright (C) 2013  Renesas Electronics Corporation
  * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
  * Copyright (C) 2002 - 2008  Paul Mundt
  *
@@ -48,7 +49,9 @@ static struct uart_port sh_sci = {
 static void sh_serial_setbrg(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
+
+	sci_out(&sh_sci, SCBRR,
+		SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ));
 }
 
 static int sh_serial_init(void)

drivers/serial/serial_sh.h

@@ -224,6 +224,9 @@ struct uart_port {
 # define SCSPTR3 0xffc60020		/* 16 bit SCIF */
 # define SCIF_ORER 0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+# define SCIF_ORER	0x0001
+# define SCSCR_INIT(port)	0x32	/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
 #else
 # error CPU subtype not defined
 #endif
@@ -298,6 +301,9 @@ struct uart_port {
 /* SH7763 SCIF2 support */
 # define SCIF2_RFDC_MASK 0x001f
 # define SCIF2_TXROOM_MAX 16
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
+# define SCIF_RFDC_MASK	0x003f
 #else
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 # define SCIF_RFDC_MASK 0x001f
@@ -579,6 +585,10 @@ SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 #else
 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 #endif
+#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+SCIF_FNS(DL,				0,  0, 0x30, 16)
+SCIF_FNS(CKS,				0,  0, 0x34, 16)
+#endif
 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 #endif
 #endif
@@ -720,6 +730,9 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#define SCBRR DL
+#define SCBRR_VALUE(bps, clk) (clk / bps / 16)
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif

include/configs/MigoR.h

@@ -123,6 +123,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ		1000
 

include/configs/ap325rxa.h

@@ -155,6 +155,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ		1000
 

include/configs/ap_sh4a_4a.h

@@ -158,6 +158,8 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 

include/configs/ecovec.h

@@ -179,6 +179,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ 41666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 

include/configs/espt.h

@@ -98,6 +98,8 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 

include/configs/mpr2.h

@@ -67,6 +67,8 @@
 
 /* Clocks */
 #define CONFIG_SYS_CLK_FREQ	24000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ		1000
 

include/configs/ms7720se.h

@@ -85,6 +85,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ		1000
 

include/configs/ms7722se.h

@@ -111,6 +111,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ		1000
 

include/configs/ms7750se.h

@@ -82,6 +82,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
 #define CONFIG_SYS_HZ		1000
 

include/configs/r0p7734.h

@@ -164,6 +164,8 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 

include/configs/r2dplus.h

@@ -77,6 +77,8 @@
  * SuperH Clock setting
  */
 #define CONFIG_SYS_CLK_FREQ	60000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
 #define CONFIG_SYS_HZ		1000
 #define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */

include/configs/r7780mp.h

@@ -102,6 +102,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
 #define CONFIG_SYS_HZ		1000
 

include/configs/rsk7203.h

@@ -85,6 +85,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ			(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 

include/configs/rsk7264.h

@@ -65,6 +65,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	36000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 

include/configs/rsk7269.h

@@ -64,6 +64,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	66125000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
 #define CONFIG_SYS_HZ		(CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
 

include/configs/sh7752evb.h

@@ -132,6 +132,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV	4
 #define CONFIG_SYS_HZ		1000
 #endif	/* __SH7752EVB_H */

include/configs/sh7757lcr.h

@@ -140,6 +140,8 @@
 
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV	4
 #define CONFIG_SYS_HZ		1000
 #endif	/* __SH7757LCR_H */

include/configs/sh7763rdp.h

@@ -98,6 +98,8 @@
 
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ		1000
 

include/configs/sh7785lcr.h

@@ -172,6 +172,8 @@
 /* Board Clock */
 /* The SCIF used external clock. system clock only used timer. */
 #define CONFIG_SYS_CLK_FREQ	50000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV		4
 #define CONFIG_SYS_HZ		1000
 

include/configs/shmin.h

@@ -103,6 +103,8 @@
 #else
 #define CONFIG_SYS_CLK_FREQ 33333333
 #endif /* CONFIG_T_SH7706LSR */
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_TMU_CLK_DIV	4
 #define CONFIG_SYS_HZ	1000
 

include/sh_tmu.h

@@ -69,7 +69,7 @@ struct tmu_regs {
 
 static inline unsigned long get_tmu0_clk_rate(void)
 {
-	return CONFIG_SYS_CLK_FREQ;
+	return CONFIG_SH_TMU_CLK_FREQ;
 }
 
 #endif	/* __SH_TMU_H */