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@@ -30,12 +30,6 @@ struct rk3288_clk_plat {
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#endif
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#endif
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};
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};
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-struct rk3288_clk_priv {
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- struct rk3288_grf *grf;
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- struct rk3288_cru *cru;
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- ulong rate;
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-};
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-
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struct pll_div {
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struct pll_div {
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u32 nr;
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u32 nr;
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u32 nf;
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u32 nf;
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@@ -140,21 +134,6 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
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-void *rockchip_get_cru(void)
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-{
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- struct rk3288_clk_priv *priv;
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- struct udevice *dev;
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- int ret;
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-
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- ret = rockchip_get_clk(&dev);
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- if (ret)
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- return ERR_PTR(ret);
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-
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- priv = dev_get_priv(dev);
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-
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- return priv->cru;
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-}
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-
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static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
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static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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const struct pll_div *div)
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{
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{
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