powerpc: ppc4xx: remove csb272, csb472 support

These have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tolunay Orkun <torkun@nextio.com>

arch/powerpc/cpu/ppc4xx/Kconfig

@@ -8,12 +8,6 @@ choice
 	prompt "Target select"
 	optional
 
-config TARGET_CSB272
-	bool "Support csb272"
-
-config TARGET_CSB472
-	bool "Support csb472"
-
 config TARGET_LWMON5
 	bool "Support lwmon5"
 	select SUPPORT_SPL
@@ -176,8 +170,6 @@ source "board/amcc/yosemite/Kconfig"
 source "board/amcc/yucca/Kconfig"
 source "board/avnet/fx12mm/Kconfig"
 source "board/avnet/v5fx30teval/Kconfig"
-source "board/csb272/Kconfig"
-source "board/csb472/Kconfig"
 source "board/esd/cpci2dp/Kconfig"
 source "board/esd/cpci405/Kconfig"
 source "board/esd/plu405/Kconfig"

board/csb272/Kconfig

@@ -1,9 +0,0 @@
-if TARGET_CSB272
-
-config SYS_BOARD
-	default "csb272"
-
-config SYS_CONFIG_NAME
-	default "csb272"
-
-endif

board/csb272/MAINTAINERS

@@ -1,6 +0,0 @@
-CSB272 BOARD
-M:	Tolunay Orkun <torkun@nextio.com>
-S:	Maintained
-F:	board/csb272/
-F:	include/configs/csb272.h
-F:	configs/csb272_defconfig

board/csb272/Makefile

@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= csb272.o
-obj-y	+= init.o

board/csb272/csb272.c

@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun@nextio.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/ppc4xx-emac.h>
-
-void sdram_init(void);
-
-/*
- * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
- *
- * CLKA output => Epson LCD Controller
- * CLKB output => Not Connected
- * CLKC output => Ethernet
- * CLKD output => UART external clock
- *
- * Note: these values are obtained from device after init by micromonitor
-*/
-uchar pll_fs6377_regs[16] = {
-	0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
-	0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
-
-/*
- * pll_init: Initialize AMIS IC FS6377-01 PLL
- *
- * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
- *
- */
-int pll_init(void)
-{
-	i2c_set_bus_num(0);
-
-	return  i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
-		(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
-}
-
-/*
- * board_early_init_f: do early board initialization
- *
- */
-int board_early_init_f(void)
-{
-	/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
-	(void) get_clocks();
-	pll_init();
-
-   /*-------------------------------------------------------------------------+
-   | Interrupt controller setup for the Walnut board.
-   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-   |       IRQ 16    405GP internally generated; active low; level sensitive
-   |       IRQ 17-24 RESERVED
-   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
-   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
-   |       IRQ 27 (EXT IRQ 2) Not Used
-   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
-   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
-   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
-   | Note for Walnut board:
-   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
-   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
-   |       interrupt. The FPGA must be read to determine which device
-   |       caused the interrupt. The default setting of the FPGA clears
-   |
-   +-------------------------------------------------------------------------*/
-
-	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
-	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
-
-	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
-
-	return 0; /* success */
-}
-
-/*
- * checkboard: identify/verify the board we are running
- *
- * Remark: we just assume it is correct board here!
- *
- */
-int checkboard(void)
-{
-	printf("BOARD: Cogent CSB272\n");
-
-	return 0; /* success */
-}
-
-/*
- * initram: Determine the size of mounted DRAM
- *
- * Size is determined by reading SDRAM configuration registers as
- * configured by initialization code
- *
- */
-phys_size_t initdram (int board_type)
-{
-	ulong tot_size;
-	ulong bank_size;
-	ulong tmp;
-
-	/*
-	 * ToDo: Move the asm init routine sdram_init() to this C file,
-	 * or even better use some common ppc4xx code available
-	 * in arch/powerpc/cpu/ppc4xx
-	 */
-	sdram_init();
-
-	tot_size = 0;
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	return tot_size;
-}
-
-/*
- * last_stage_init: final configurations (such as PHY etc)
- *
- */
-int last_stage_init(void)
-{
-	/* initialize the PHY */
-	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
-
-	/* AUTO neg */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
-	/* LEDs     */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
-
-
-	return 0; /* success */
-}

board/csb272/init.S

@@ -1,196 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define LI32(reg,val) \
-	addis   reg,0,val@h;\
-	ori     reg,reg,val@l
-
-#define WDCR_EBC(reg,val) \
-	addi    r4,0,reg;\
-	mtdcr   EBC0_CFGADDR,r4;\
-	addis   r4,0,val@h;\
-	ori     r4,r4,val@l;\
-	mtdcr   EBC0_CFGDATA,r4
-
-#define WDCR_SDRAM(reg,val) \
-	addi    r4,0,reg;\
-	mtdcr   SDRAM0_CFGADDR,r4;\
-	addis   r4,0,val@h;\
-	ori     r4,r4,val@l;\
-	mtdcr   SDRAM0_CFGDATA,r4
-
-/******************************************************************************
- * Function:	ext_bus_cntlr_init
- *
- * Description:	Configures EBC Controller and a few basic chip selects.
- *
- *		CS0 is setup to get the Boot Flash out of the addresss range
- *		so that we may setup a stack.  CS7 is setup so that we can
- *		access and reset the hardware watchdog.
- *
- *		IMPORTANT: For pass1 this code must run from
- *		cache since you can not reliably change a peripheral banks
- *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT
- *		execute the code that modifies bank 0 timings from ROM, so
- *		we run it from cache.
- *
- * Notes:	Does NOT use the stack.
- *****************************************************************************/
-	.section ".text"
-	.align	2
-	.globl	ext_bus_cntlr_init
-	.type	ext_bus_cntlr_init, @function
-ext_bus_cntlr_init:
-	mflr	r0
-	/********************************************************************
-	 * Prefetch entire ext_bus_cntrl_init function into the icache.
-	 * This is necessary because we are going to change the same CS we
-	 * are executing from.  Otherwise a CPU lockup may occur.
-	 *******************************************************************/
-	bl	..getAddr
-..getAddr:
-	mflr	r3			/* get address of ..getAddr */
-
-	/* Calculate number of cache lines for this function */
-	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
-	mtctr	r4
-..ebcloop:
-	icbt	r0, r3			/* prefetch cache line for addr in r3*/
-	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
-	bdnz	..ebcloop		/* continue for $CTR cache lines */
-
-	/********************************************************************
-	 * Delay to ensure all accesses to ROM are complete before changing
-	 * bank 0 timings. 200usec should be enough.
-	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
-	 *******************************************************************/
-	addis	r3, 0, 0x0
-	ori	r3, r3, 0xA000		/* wait 200us from reset */
-	mtctr	r3
-..spinlp:
-	bdnz	..spinlp		/* spin loop */
-
-	/********************************************************************
-	 * SETUP CPC0_CR0
-	 *******************************************************************/
-	LI32(r4, 0x007000c0)
-	mtdcr	CPC0_CR0, r4
-
-	/********************************************************************
-	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
-	 *******************************************************************/
-	mfdcr	r4, CPC0_CR1
-	ori	r4, r4, 0x4000
-	mtdcr	CPC0_CR1, r4
-
-	/********************************************************************
-	 * Setup External Bus Controller (EBC).
-	 *******************************************************************/
-	WDCR_EBC(EBC0_CFG, 0xd84c0000)
-	/********************************************************************
-	 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
-	 *******************************************************************/
-	/*WDCR_EBC(PB1AP, 0x02869200)*/
-	WDCR_EBC(PB1AP, 0x07869200)
-	WDCR_EBC(PB0CR, 0xfe0bc000)
-	/********************************************************************
-	 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
-	 *******************************************************************/
-	WDCR_EBC(PB1AP, 0x1f869200)
-	WDCR_EBC(PB1CR, 0xf0818000)
-	/********************************************************************
-	 * Memory Bank 2 (Epson S1D13506) initialization
-	 *******************************************************************/
-	WDCR_EBC(PB2AP, 0x05860300)
-	WDCR_EBC(PB2CR, 0xf045a000)
-	/********************************************************************
-	 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
-	 *******************************************************************/
-	WDCR_EBC(PB3AP, 0x0387d200)
-	WDCR_EBC(PB3CR, 0xf021c000)
-	/********************************************************************
-	 * Memory Bank 4-7 (Unused) initialization
-	 *******************************************************************/
-	WDCR_EBC(PB4AP, 0)
-	WDCR_EBC(PB4CR, 0)
-	WDCR_EBC(PB5AP, 0)
-	WDCR_EBC(PB5CR, 0)
-	WDCR_EBC(PB6AP, 0)
-	WDCR_EBC(PB6CR, 0)
-	WDCR_EBC(PB7AP, 0)
-	WDCR_EBC(PB7CR, 0)
-
-	/* We are all done */
-	mtlr	r0			/* Restore link register */
-	blr				/* Return to calling function */
-.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
-/* end ext_bus_cntlr_init() */
-
-/******************************************************************************
- * Function:	sdram_init
- *
- * Description:	Configures SDRAM memory banks.
- *
- * Notes:	Does NOT use the stack.
- *****************************************************************************/
-	.section ".text"
-	.align	2
-	.globl	sdram_init
-	.type	sdram_init, @function
-sdram_init:
-
-	/*
-	 * Disable memory controller to allow
-	 * values to be changed.
-	 */
-	WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
-
-	/*
-	 * Configure Memory Banks
-	 */
-	WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
-	WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
-	WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
-	WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
-
-	/*
-	 * Set up SDTR1 (SDRAM Timing Register)
-	 */
-	WDCR_SDRAM(SDRAM0_TR, 0x00854009)
-
-	/*
-	 * Set RTR (Refresh Timing Register)
-	 */
-	WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
-	/* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */
-
-	/********************************************************************
-	 * Delay to ensure 200usec have elapsed since reset. Assume worst
-	 * case that the core is running 200Mhz:
-	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
-	 *******************************************************************/
-	addis   r3, 0, 0x0000
-	ori     r3, r3, 0xA000		/* Wait >200us from reset */
-	mtctr   r3
-..spinlp2:
-	bdnz    ..spinlp2		/* spin loop */
-
-	/********************************************************************
-	 * Set memory controller options reg, MCOPT1.
-	 *******************************************************************/
-	WDCR_SDRAM(SDRAM0_CFG,0x80800000)
-
-..sdri_done:
-	blr				/* Return to calling function */
-.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
-/* end sdram_init() */

board/csb472/Kconfig

@@ -1,9 +0,0 @@
-if TARGET_CSB472
-
-config SYS_BOARD
-	default "csb472"
-
-config SYS_CONFIG_NAME
-	default "csb472"
-
-endif

board/csb472/MAINTAINERS

@@ -1,6 +0,0 @@
-CSB472 BOARD
-M:	Tolunay Orkun <torkun@nextio.com>
-S:	Maintained
-F:	board/csb472/
-F:	include/configs/csb472.h
-F:	configs/csb472_defconfig

board/csb472/Makefile

@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= csb472.o
-obj-y	+= init.o

board/csb472/csb472.c

@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun@nextio.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/ppc4xx-emac.h>
-
-void sdram_init(void);
-
-/*
- * board_early_init_f: do early board initialization
- *
- */
-int board_early_init_f(void)
-{
-   /*-------------------------------------------------------------------------+
-   | Interrupt controller setup for the Walnut board.
-   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-   |       IRQ 16    405GP internally generated; active low; level sensitive
-   |       IRQ 17-24 RESERVED
-   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
-   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
-   |       IRQ 27 (EXT IRQ 2) Not Used
-   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
-   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
-   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
-   | Note for Walnut board:
-   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
-   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
-   |       interrupt. The FPGA must be read to determine which device
-   |       caused the interrupt. The default setting of the FPGA clears
-   |
-   +-------------------------------------------------------------------------*/
-
-	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
-	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
-
-	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
-
-	return 0; /* success */
-}
-
-/*
- * checkboard: identify/verify the board we are running
- *
- * Remark: we just assume it is correct board here!
- *
- */
-int checkboard(void)
-{
-	printf("BOARD: Cogent CSB472\n");
-
-	return 0; /* success */
-}
-
-/*
- * initram: Determine the size of mounted DRAM
- *
- * Size is determined by reading SDRAM configuration registers as
- * configured by initialization code
- *
- */
-phys_size_t initdram (int board_type)
-{
-	ulong tot_size;
-	ulong bank_size;
-	ulong tmp;
-
-	/*
-	 * ToDo: Move the asm init routine sdram_init() to this C file,
-	 * or even better use some common ppc4xx code available
-	 * in arch/powerpc/cpu/ppc4xx
-	 */
-	sdram_init();
-
-	tot_size = 0;
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	return tot_size;
-}
-
-/*
- * last_stage_init: final configurations (such as PHY etc)
- *
- */
-int last_stage_init(void)
-{
-	/* initialize the PHY */
-	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
-
-	/* AUTO neg */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
-	/* LEDs     */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
-
-	return 0; /* success */
-}

board/csb472/init.S

@@ -1,192 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define LI32(reg,val) \
-	addis   reg,0,val@h;\
-	ori     reg,reg,val@l
-
-#define WDCR_EBC(reg,val) \
-	addi    r4,0,reg;\
-	mtdcr   EBC0_CFGADDR,r4;\
-	addis   r4,0,val@h;\
-	ori     r4,r4,val@l;\
-	mtdcr   EBC0_CFGDATA,r4
-
-#define WDCR_SDRAM(reg,val) \
-	addi    r4,0,reg;\
-	mtdcr   SDRAM0_CFGADDR,r4;\
-	addis   r4,0,val@h;\
-	ori     r4,r4,val@l;\
-	mtdcr   SDRAM0_CFGDATA,r4
-
-/******************************************************************************
- * Function:	ext_bus_cntlr_init
- *
- * Description:	Configures EBC Controller and a few basic chip selects.
- *
- *		CS0 is setup to get the Boot Flash out of the addresss range
- *		so that we may setup a stack.  CS7 is setup so that we can
- *		access and reset the hardware watchdog.
- *
- *		IMPORTANT: For pass1 this code must run from
- *		cache since you can not reliably change a peripheral banks
- *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT
- *		execute the code that modifies bank 0 timings from ROM, so
- *		we run it from cache.
- *
- * Notes:	Does NOT use the stack.
- *****************************************************************************/
-	.section ".text"
-	.align	2
-	.globl	ext_bus_cntlr_init
-	.type	ext_bus_cntlr_init, @function
-ext_bus_cntlr_init:
-	mflr	r0
-	/********************************************************************
-	 * Prefetch entire ext_bus_cntrl_init function into the icache.
-	 * This is necessary because we are going to change the same CS we
-	 * are executing from.  Otherwise a CPU lockup may occur.
-	 *******************************************************************/
-	bl	..getAddr
-..getAddr:
-	mflr	r3			/* get address of ..getAddr */
-
-	/* Calculate number of cache lines for this function */
-	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
-	mtctr	r4
-..ebcloop:
-	icbt	r0, r3			/* prefetch cache line for addr in r3*/
-	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
-	bdnz	..ebcloop		/* continue for $CTR cache lines */
-
-	/********************************************************************
-	 * Delay to ensure all accesses to ROM are complete before changing
-	 * bank 0 timings. 200usec should be enough.
-	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
-	 *******************************************************************/
-	addis	r3, 0, 0x0
-	ori	r3, r3, 0xA000		/* wait 200us from reset */
-	mtctr	r3
-..spinlp:
-	bdnz	..spinlp		/* spin loop */
-
-	/********************************************************************
-	 * SETUP CPC0_CR0
-	 *******************************************************************/
-	LI32(r4, 0x00c01030)
-	mtdcr	CPC0_CR0, r4
-
-	/********************************************************************
-	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
-	 *******************************************************************/
-	mfdcr	r4, CPC0_CR1
-	ori	r4, r4, 0x4000
-	mtdcr	CPC0_CR1, r4
-
-	/********************************************************************
-	 * Setup External Bus Controller (EBC).
-	 *******************************************************************/
-	WDCR_EBC(EBC0_CFG, 0xd84c0000)
-	/********************************************************************
-	 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
-	 *******************************************************************/
-	/*WDCR_EBC(PB1AP, 0x03055200)*/
-	/*WDCR_EBC(PB1AP, 0x04055200)*/
-	WDCR_EBC(PB1AP, 0x08055200)
-	WDCR_EBC(PB0CR, 0xff87a000)
-	/********************************************************************
-	 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
-	 *******************************************************************/
-	/*WDCR_EBC(PB3AP, 0x07869200)*/
-	WDCR_EBC(PB3AP, 0x04055200)
-	WDCR_EBC(PB3CR, 0xf081c000)
-	/********************************************************************
-	 * Memory Bank 1,2,4-7 (Unused) initialization
-	 *******************************************************************/
-	WDCR_EBC(PB1AP, 0)
-	WDCR_EBC(PB1CR, 0)
-	WDCR_EBC(PB2AP, 0)
-	WDCR_EBC(PB2CR, 0)
-	WDCR_EBC(PB4AP, 0)
-	WDCR_EBC(PB4CR, 0)
-	WDCR_EBC(PB5AP, 0)
-	WDCR_EBC(PB5CR, 0)
-	WDCR_EBC(PB6AP, 0)
-	WDCR_EBC(PB6CR, 0)
-	WDCR_EBC(PB7AP, 0)
-	WDCR_EBC(PB7CR, 0)
-
-	/* We are all done */
-	mtlr	r0			/* Restore link register */
-	blr				/* Return to calling function */
-.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
-/* end ext_bus_cntlr_init() */
-
-/******************************************************************************
- * Function:	sdram_init
- *
- * Description:	Configures SDRAM memory banks.
- *
- * Notes:	Does NOT use the stack.
- *****************************************************************************/
-	.section ".text"
-	.align	2
-	.globl	sdram_init
-	.type	sdram_init, @function
-sdram_init:
-
-	/*
-	 * Disable memory controller to allow
-	 * values to be changed.
-	 */
-	WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
-
-	/*
-	 * Configure Memory Banks
-	 */
-	WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
-	WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
-	WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
-	WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
-
-	/*
-	 * Set up SDTR1 (SDRAM Timing Register)
-	 */
-	WDCR_SDRAM(SDRAM0_TR, 0x00854009)
-
-	/*
-	 * Set RTR (Refresh Timing Register)
-	 */
-	WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
-	/* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */
-
-	/********************************************************************
-	 * Delay to ensure 200usec have elapsed since reset. Assume worst
-	 * case that the core is running 200Mhz:
-	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
-	 *******************************************************************/
-	addis   r3, 0, 0x0000
-	ori     r3, r3, 0xA000		/* Wait >200us from reset */
-	mtctr   r3
-..spinlp2:
-	bdnz    ..spinlp2		/* spin loop */
-
-	/********************************************************************
-	 * Set memory controller options reg, MCOPT1.
-	 *******************************************************************/
-	WDCR_SDRAM(SDRAM0_CFG,0x80800000)
-
-..sdri_done:
-	blr				/* Return to calling function */
-.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
-/* end sdram_init() */

configs/csb272_defconfig

@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CSB272=y
-# CONFIG_CMD_SETEXPR is not set

configs/csb472_defconfig

@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CSB472=y
-# CONFIG_CMD_SETEXPR is not set

doc/README.scrapyard

@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+csb272/csb472    powerpc     ppc4xx         -           -           Tolunay Orkun <torkun@nextio.com>
 alpr             powerpc     ppc4xx         -           -           Stefan Roese <sr@denx.de>
 cam_enc_4xx      arm         arm926ejs      8d775763    2015-08-20  Heiko Schocher <hs@denx.de>
 atstk1003        avr32       -              e5354b8a    2015-06-10  Haavard Skinnemoen <haavard.skinnemoen@atmel.com>

include/configs/csb272.h

@@ -1,282 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun@nextio.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
-#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
-#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * OS Bootstrap configuration
- *
- */
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
-#endif
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */
-
-#if 1
-#undef  CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
-	"setenv bootargs console=ttyS0,38400 debug " \
-	"root=/dev/ram rw ramdisk_size=4096 " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm fe000000 fe100000"
-#endif
-
-#if 0
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
-	"bootp; " \
-	"setenv bootargs console=ttyS0,38400 debug " \
-	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm"
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-
-/*
- * Serial download configuration
- *
- */
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-/*
- * KGDB Configuration
- *
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- *
- */
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
-#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*
- * watchdog configuration
- *
- */
-#undef  CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * UART configuration
- *
- */
-#define CONFIG_CONS_INDEX		1	/* Use UART0		*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
-#undef  CONFIG_SYS_BASE_BAUD
-#define CONFIG_BAUDRATE		38400	/* Default baud rate */
-#define CONFIG_SYS_BAUDRATE_TABLE      \
-    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * I2C configuration
- *
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F	/* I2C slave address */
-
-/*
- * MII PHY configuration
- *
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
-					/* 32usec min. for LXT971A	*/
-#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
-
-/*
- * RTC configuration
- *
- * Note that DS1307 RTC is limited to 100Khz I2C bus.
- *
- */
-#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/
-
-/*
- * PCI stuff
- *
- */
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
-#define PCI_HOST_FORCE		1	/* configure as pci host        */
-#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
-
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
-#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*
- * IDE stuff
- *
- */
-#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
-
-/*
- * Environment configuration
- *
- */
-#define CONFIG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-
-/*
- * General Memory organization
- *
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_RAMSTART
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-#define CONFIG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
-#define CONFIG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
-#define	CONFIG_ENV_SIZE		0x00001000 /* Size of Environment */
-#define CONFIG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
-#endif
-
-/*
- * FLASH Device configuration
- *
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
-#define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
-#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-/*
- * On Chip Memory location/size
- *
- */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-/*
- * Global info and initial stack
- *
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Miscellaneous board specific definitions
- *
- */
-#define CONFIG_SYS_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
-#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */
-
-#endif	/* __CONFIG_H */

include/configs/csb472.h

@@ -1,281 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun@nextio.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
-#define CONFIG_CSB472		1	/* on a Cogent CSB472 board     */
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
-#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-/*
- * OS Bootstrap configuration
- *
- */
-
-#if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
-#endif
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */
-
-#if 1
-#undef  CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
-	"setenv bootargs console=ttyS0,38400 debug " \
-	"root=/dev/ram rw ramdisk_size=4096 " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm ff800000 ff900000"
-#endif
-
-#if 0
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
-	"bootp; " \
-	"setenv bootargs console=ttyS0,38400 debug " \
-	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
-	"bootm"
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS2
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-
-/*
- * Serial download configuration
- *
- */
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-/*
- * KGDB Configuration
- *
- */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Miscellaneous configurable options
- *
- */
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
-
-#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
-#if defined(CONFIG_CMD_KGDB)
-#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
-#else
-#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
-#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
-
-/*
- * watchdog configuration
- *
- */
-#undef  CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * UART configuration
- *
- */
-#define CONFIG_CONS_INDEX		1	/* Use UART0		*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* use internal serial clock */
-#define CONFIG_SYS_BASE_BAUD		691200
-#define CONFIG_BAUDRATE		38400	/* Default baud rate */
-#define CONFIG_SYS_BAUDRATE_TABLE      \
-    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * I2C configuration
- *
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F	/* I2C slave address */
-
-/*
- * MII PHY configuration
- *
- */
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
-					/* 32usec min. for LXT971A	*/
-#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
-
-/*
- * RTC configuration
- *
- * Note that DS1307 RTC is limited to 100Khz I2C bus.
- *
- */
-#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/
-
-/*
- * PCI stuff
- *
- */
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
-#define PCI_HOST_FORCE		1	/* configure as pci host        */
-#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
-
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
-					/* resource configuration       */
-#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
-#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*
- * IDE stuff
- *
- */
-#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
-
-/*
- * Environment configuration
- *
- */
-#define CONFIG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-
-/*
- * General Memory organization
- *
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFF800000
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
-
-#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_RAMSTART
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-#define CONFIG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
-#define CONFIG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
-#define	CONFIG_ENV_SIZE		0x00001000 /* Size of Environment */
-#define CONFIG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
-#endif
-
-/*
- * FLASH Device configuration
- *
- */
-#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
-#define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
-#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max # of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-/*
- * On Chip Memory location/size
- *
- */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-/*
- * Global info and initial stack
- *
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Miscellaneous board specific definitions
- *
- */
-#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */
-
-#endif	/* __CONFIG_H */