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@@ -1,129 +0,0 @@
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-/*
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- * Copyright (C) 2016 Amarula Solutions B.V.
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- * Copyright (C) 2016 Engicam S.r.l.
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- * Author: Jagan Teki <jagan@amarulasolutions.com>
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- *
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- * SPDX-License-Identifier: GPL-2.0+
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- */
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-
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-#include <common.h>
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-#include <mmc.h>
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-
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-#include <asm/io.h>
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-#include <asm/gpio.h>
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-#include <linux/sizes.h>
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-
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-#include <asm/arch/clock.h>
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-#include <asm/arch/crm_regs.h>
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-#include <asm/arch/iomux.h>
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-#include <asm/arch/mx6-pins.h>
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-#include <asm/arch/sys_proto.h>
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-#include <asm/mach-imx/iomux-v3.h>
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-
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-#include "../common/board.h"
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-
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-DECLARE_GLOBAL_DATA_PTR;
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-
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-#ifdef CONFIG_NAND_MXS
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-
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-#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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-#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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- PAD_CTL_SRE_FAST)
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-#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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-
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-static iomux_v3_cfg_t const nand_pads[] = {
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- IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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- IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
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-};
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-
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-void setup_gpmi_nand(void)
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-{
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- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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-
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- /* config gpmi nand iomux */
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- SETUP_IOMUX_PADS(nand_pads);
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-
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- clrbits_le32(&mxc_ccm->CCGR4,
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- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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-
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- /*
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- * config gpmi and bch clock to 100 MHz
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- * bch/gpmi select PLL2 PFD2 400M
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- * 100M = 400M / 4
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- */
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- clrbits_le32(&mxc_ccm->cscmr1,
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- MXC_CCM_CSCMR1_BCH_CLK_SEL |
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- MXC_CCM_CSCMR1_GPMI_CLK_SEL);
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- clrsetbits_le32(&mxc_ccm->cscdr1,
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- MXC_CCM_CSCDR1_BCH_PODF_MASK |
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- MXC_CCM_CSCDR1_GPMI_PODF_MASK,
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- (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
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- (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
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-
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- /* enable gpmi and bch clock gating */
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- setbits_le32(&mxc_ccm->CCGR4,
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- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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-
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- /* enable apbh clock gating */
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- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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-}
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-#endif /* CONFIG_NAND_MXS */
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-
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-#ifdef CONFIG_ENV_IS_IN_MMC
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-int board_mmc_get_env_dev(int devno)
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-{
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- /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
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- return (devno == 0) ? 0 : 1;
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-}
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-#endif
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-
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-#ifdef CONFIG_SPL_BUILD
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-#include <spl.h>
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-
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-#ifdef CONFIG_ENV_IS_IN_MMC
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-void board_boot_order(u32 *spl_boot_list)
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-{
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- u32 bmode = imx6_src_get_boot_mode();
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- u8 boot_dev = BOOT_DEVICE_MMC1;
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-
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- switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
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- case IMX6_BMODE_SD:
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- case IMX6_BMODE_ESD:
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- /* SD/eSD - BOOT_DEVICE_MMC1 */
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- break;
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- case IMX6_BMODE_MMC:
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- case IMX6_BMODE_EMMC:
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- /* MMC/eMMC */
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- boot_dev = BOOT_DEVICE_MMC2;
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- break;
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- default:
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- /* Default - BOOT_DEVICE_MMC1 */
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- printf("Wrong board boot order\n");
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- break;
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- }
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-
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- spl_boot_list[0] = boot_dev;
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-}
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-#endif
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-#endif /* CONFIG_SPL_BUILD */
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