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@@ -1,6 +1,7 @@
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/*
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/*
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* LayerScape Internal Memory Map
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* LayerScape Internal Memory Map
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*
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*
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+ * Copyright (C) 2017 NXP Semiconductors
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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@@ -45,6 +46,9 @@
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#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
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#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
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#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
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#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
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#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
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#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
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+#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
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+#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
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+#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
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#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
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#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
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#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
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#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
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