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@@ -166,6 +166,9 @@ DECLARE_GLOBAL_DATA_PTR;
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#define RP_VEND_XP 0x00000F00
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#define RP_VEND_XP_DL_UP (1 << 30)
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+#define RP_VEND_CTL2 0x00000FA8
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+#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
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+
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#define RP_PRIV_MISC 0x00000FE0
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#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
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#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
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@@ -194,6 +197,7 @@ struct tegra_pcie_soc {
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bool has_pex_bias_ctrl;
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bool has_cml_clk;
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bool has_gen2;
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+ bool force_pca_enable;
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};
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struct tegra_pcie {
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@@ -887,6 +891,7 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
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static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
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{
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+ const struct tegra_pcie_soc *soc = port->pcie->soc;
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unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
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unsigned long value;
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@@ -902,6 +907,12 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
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afi_writel(port->pcie, value, ctrl);
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tegra_pcie_port_reset(port);
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+
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+ if (soc->force_pca_enable) {
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+ value = rp_readl(port, RP_VEND_CTL2);
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+ value |= RP_VEND_CTL2_PCA_ENABLE;
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+ rp_writel(port, value, RP_VEND_CTL2);
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+ }
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}
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static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
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@@ -999,6 +1010,7 @@ static const struct tegra_pcie_soc tegra20_pcie_soc = {
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.has_pex_bias_ctrl = false,
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.has_cml_clk = false,
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.has_gen2 = false,
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+ .force_pca_enable = false,
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};
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static const struct tegra_pcie_soc tegra30_pcie_soc = {
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@@ -1009,6 +1021,7 @@ static const struct tegra_pcie_soc tegra30_pcie_soc = {
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = false,
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+ .force_pca_enable = false,
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};
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static const struct tegra_pcie_soc tegra124_pcie_soc = {
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@@ -1019,6 +1032,7 @@ static const struct tegra_pcie_soc tegra124_pcie_soc = {
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.has_pex_bias_ctrl = true,
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.has_cml_clk = true,
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.has_gen2 = true,
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+ .force_pca_enable = false,
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};
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static int process_nodes(const void *fdt, int nodes[], unsigned int count)
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