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@@ -26,6 +26,12 @@
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#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
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#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
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+#define SNVS_LPCR 0x38
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+#define BP_SNVS_LPCR_DP_EN 0x20
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+#define BP_SNVS_LPCR_TOP 0x40
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+
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+#define CCM_CCGR_SNVS 0x4250
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+
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#define CCM_ROOT_WDOG 0xbb80
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#define CCM_CCGR_WDOG1 0x49c0
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@@ -87,3 +93,15 @@ __secure void imx_system_reset(void)
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writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
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writew(WCR_WDE, &wdog->wcr);
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}
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+
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+__secure void imx_system_off(void)
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+{
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+ u32 val;
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+
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+ /* make sure SNVS clock is enabled */
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+ writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
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+
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+ val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
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+ val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
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+ writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
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+}
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