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+/*
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+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <asm/arch/freeze_controller.h>
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+#include <asm/arch/timer.h>
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+#include <asm/errno.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+static const struct socfpga_freeze_controller *freeze_controller_base =
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+ (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
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+
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+/*
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+ * Default state from cold reset is FREEZE_ALL; the global
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+ * flag is set to TRUE to indicate the IO banks are frozen
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+ */
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+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
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+ = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
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+ FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
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+
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+/* Freeze HPS IOs */
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+void sys_mgr_frzctrl_freeze_req(void)
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+{
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+ u32 ioctrl_reg_offset;
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+ u32 reg_value;
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+ u32 reg_cfg_mask;
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+ u32 channel_id;
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+
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+ /* select software FSM */
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+ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
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+
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+ /* Freeze channel 0 to 2 */
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+ for (channel_id = 0; channel_id <= 2; channel_id++) {
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+ ioctrl_reg_offset = (u32)(
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+ &freeze_controller_base->vioctrl +
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+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
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+
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+ /*
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+ * Assert active low enrnsl, plniotri
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+ * and niotri signals
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+ */
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+ reg_cfg_mask =
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+ SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
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+ | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
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+ | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
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+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
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+
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+ /*
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+ * Note: Delay for 20ns at min
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+ * Assert active low bhniotri signal and de-assert
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+ * active high csrdone
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+ */
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+ reg_cfg_mask
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+ = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
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+ | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
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+ clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
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+
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+ /* Set global flag to indicate channel is frozen */
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+ frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
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+ }
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+
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+ /* Freeze channel 3 */
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+ /*
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+ * Assert active low enrnsl, plniotri and
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+ * niotri signals
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+ */
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+ reg_cfg_mask
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+ = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
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+ | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
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+ | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
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+ clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
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+
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+ /*
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+ * assert active low bhniotri & nfrzdrv signals,
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+ * de-assert active high csrdone and assert
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+ * active high frzreg and nfrzdrv signals
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+ */
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+ reg_value = readl(&freeze_controller_base->hioctrl);
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+ reg_cfg_mask
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+ = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
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+ | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
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+ reg_value
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+ = (reg_value & ~reg_cfg_mask)
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+ | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
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+ | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
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+ writel(reg_value, &freeze_controller_base->hioctrl);
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+
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+ /*
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+ * assert active high reinit signal and de-assert
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+ * active high pllbiasen signals
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+ */
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+ reg_value = readl(&freeze_controller_base->hioctrl);
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+ reg_value
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+ = (reg_value &
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+ ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
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+ | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
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+ writel(reg_value, &freeze_controller_base->hioctrl);
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+
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+ /* Set global flag to indicate channel is frozen */
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+ frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
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+}
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+
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+/* Unfreeze/Thaw HPS IOs */
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+void sys_mgr_frzctrl_thaw_req(void)
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+{
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+ u32 ioctrl_reg_offset;
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+ u32 reg_cfg_mask;
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+ u32 reg_value;
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+ u32 channel_id;
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+
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+ /* select software FSM */
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+ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
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+
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+ /* Thaw channel 0 to 2 */
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+ for (channel_id = 0; channel_id <= 2; channel_id++) {
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+ ioctrl_reg_offset
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+ = (u32)(&freeze_controller_base->vioctrl
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+ + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
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+
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+ /*
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+ * Assert active low bhniotri signal and
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+ * de-assert active high csrdone
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+ */
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+ reg_cfg_mask
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+ = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
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+ | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
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+ setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
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+
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+ /*
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+ * Note: Delay for 20ns at min
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+ * de-assert active low plniotri and niotri signals
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+ */
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+ reg_cfg_mask
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+ = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
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+ | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
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+ setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
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+
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+ /*
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+ * Note: Delay for 20ns at min
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+ * de-assert active low enrnsl signal
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+ */
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+ setbits_le32(ioctrl_reg_offset,
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+ SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
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+
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+ /* Set global flag to indicate channel is thawed */
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+ frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
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+ }
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+
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+ /* Thaw channel 3 */
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+ /* de-assert active high reinit signal */
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+ clrbits_le32(&freeze_controller_base->hioctrl,
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+ SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
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+
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+ /*
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+ * Note: Delay for 40ns at min
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+ * assert active high pllbiasen signals
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+ */
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+ setbits_le32(&freeze_controller_base->hioctrl,
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+ SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
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+
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+ /*
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+ * Delay 1000 intosc. intosc is based on eosc1
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+ * Use worst case which is fatest eosc1=50MHz, delay required
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+ * is 1/50MHz * 1000 = 20us
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+ */
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+ udelay(20);
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+
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+ /*
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+ * de-assert active low bhniotri signals,
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+ * assert active high csrdone and nfrzdrv signal
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+ */
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+ reg_value = readl(&freeze_controller_base->hioctrl);
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+ reg_value = (reg_value
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+ | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
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+ | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
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+ & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
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+ writel(reg_value, &freeze_controller_base->hioctrl);
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+
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+ /*
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+ * Delay 33 intosc
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+ * Use worst case which is fatest eosc1=50MHz, delay required
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+ * is 1/50MHz * 33 = 660ns ~= 1us
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+ */
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+ udelay(1);
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+
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+ /* de-assert active low plniotri and niotri signals */
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+ reg_cfg_mask
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+ = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
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+ | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
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+
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+ setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
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+
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+ /*
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+ * Note: Delay for 40ns at min
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+ * de-assert active high frzreg signal
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+ */
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+ clrbits_le32(&freeze_controller_base->hioctrl,
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+ SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
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+
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+ /*
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+ * Note: Delay for 40ns at min
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+ * de-assert active low enrnsl signal
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+ */
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+ setbits_le32(&freeze_controller_base->hioctrl,
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+ SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
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+
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+ /* Set global flag to indicate channel is thawed */
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+ frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
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+}
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