arm: socfpga: misc: Add proper ethernet initialization

Add function to initialize the EMAC blocks upon board startup.
The preprocessor guards against building on SoCFPGA-VT and against
SPL build are not needed as those are handled implicitly via both
SPL framework and the socfpga_cyclone5.h config file, which will
not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT.

We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs.
Once there is hardware using both EMAC blocks, this ifdef will have
to go.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

arch/arm/cpu/armv7/socfpga/misc.c

@@ -9,15 +9,58 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct socfpga_system_manager *sysmgr_regs =
+	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
 
+/*
+ * DesignWare Ethernet initialization
+ */
+#ifdef CONFIG_DESIGNWARE_ETH
+int cpu_eth_init(bd_t *bis)
+{
+#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
+	const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+#else
+#error "Incorrect CONFIG_EMAC_BASE value!"
+#endif
+
+	/* Initialize EMAC. This needs to be done at least once per boot. */
+
+	/*
+	 * Putting the EMAC controller to reset when configuring the PHY
+	 * interface select at System Manager
+	 */
+	socfpga_emac_reset(1);
+
+	/* Clearing emac0 PHY interface select to 0 */
+	clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
+
+	/* configure to PHY interface select choosed */
+	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
+		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+
+	/* Release the EMAC controller from reset */
+	socfpga_emac_reset(0);
+
+	/* initialize and register the emac */
+	return designware_initialize(CONFIG_EMAC_BASE,
+				     CONFIG_PHY_INTERFACE_MODE);
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 /*
  * Print CPU information
@@ -54,18 +97,3 @@ int misc_init_r(void)
 {
 	return 0;
 }
-
-
-/*
- * DesignWare Ethernet initialization
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) && !defined(CONFIG_SPL_BUILD)
-       /* initialize and register the emac */
-	return designware_initialize(CONFIG_EMAC_BASE,
-				     CONFIG_PHY_INTERFACE_MODE);
-#else
-	return 0;
-#endif
-}

arch/arm/include/asm/arch-socfpga/system_manager.h

@@ -134,4 +134,13 @@ struct socfpga_system_manager {
 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
 	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
 
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII		0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII		0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB			0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
+
 #endif /* _SYSTEM_MANAGER_H_ */