ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.c

Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
the two dwc3 controllers present in dra7xx/am43xx and enabled these
clocks in enable_basic_clocks() in hw_data.c. However these clocks
continued to be enabled in board files/driver files for dwc3 host
mode functionality causing compilation break with few configs.

Fixed it here by making all the clocks enabled in enable_basic_clocks()
and removing it from board files/driver files here.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

arch/arm/cpu/armv7/omap5/hw_data.c

@@ -460,7 +460,7 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_l4per_gpio6_clkctrl,
 		(*prcm)->cm_l4per_gpio7_clkctrl,
 		(*prcm)->cm_l4per_gpio8_clkctrl,
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
 		(*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 #endif
@@ -495,7 +495,7 @@ void enable_basic_clocks(void)
 	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 	/* Enable 960 MHz clock for dwc3 */
 	setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 		     OPTFCLKEN_REFCLK960M);

board/ti/beagle_x15/board.c

@@ -385,13 +385,3 @@ int board_eth_init(bd_t *bis)
 	return ret;
 }
 #endif
-
-#ifdef CONFIG_USB_XHCI_OMAP
-int board_usb_init(int index, enum usb_init_type init)
-{
-	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
-			OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
-
-	return 0;
-}
-#endif

drivers/usb/phy/omap_usb_phy.c

@@ -131,17 +131,6 @@ static void omap_enable_usb3_phy(struct omap_xhci *omap)
 {
 	u32	val;
 
-	/* Setting OCP2SCP1 register */
-	setbits_le32((*prcm)->cm_l3init_ocp2scp1_clkctrl,
-		     OCP2SCP1_CLKCTRL_MODULEMODE_HW);
-
-	/* Turn on 32K AON clk */
-	setbits_le32((*prcm)->cm_coreaon_usb_phy_core_clkctrl,
-		     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
-
-	/* Setting CM_L3INIT_CLKSTCTRL to 0x0 i.e NO sleep */
-	writel(0x0, (*prcm)->cm_l3init_clkstctrl);
-
 	val = (USBOTGSS_DMADISABLE |
 			USBOTGSS_STANDBYMODE_SMRT_WKUP |
 			USBOTGSS_IDLEMODE_NOIDLE);
@@ -169,11 +158,6 @@ static void omap_enable_usb3_phy(struct omap_xhci *omap)
 	writel(val, &omap->otg_wrapper->irqstatus_1);
 	val = readl(&omap->otg_wrapper->irqstatus_0);
 	writel(val, &omap->otg_wrapper->irqstatus_0);
-
-	/* Enable the USB OTG Super speed clocks */
-	val = (OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW);
-	setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, val);
-
 };
 #endif /* CONFIG_OMAP_USB3PHY1_HOST */