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@@ -513,16 +513,19 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
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switch (periph) {
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case HCLK_EMMC:
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+ case SCLK_EMMC:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
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div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
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break;
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case HCLK_SDMMC:
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+ case SCLK_SDMMC:
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con = readl(&cru->cru_clksel_con[11]);
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mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
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div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
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break;
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case HCLK_SDIO0:
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+ case SCLK_SDIO0:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
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div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
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@@ -556,6 +559,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
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}
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switch (periph) {
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case HCLK_EMMC:
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+ case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_PLL_MASK << EMMC_PLL_SHIFT |
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EMMC_DIV_MASK << EMMC_DIV_SHIFT,
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@@ -563,6 +567,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
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(src_clk_div - 1) << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDMMC:
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+ case SCLK_SDMMC:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_PLL_MASK << MMC0_PLL_SHIFT |
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MMC0_DIV_MASK << MMC0_DIV_SHIFT,
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@@ -570,6 +575,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
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(src_clk_div - 1) << MMC0_DIV_SHIFT);
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break;
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case HCLK_SDIO0:
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+ case SCLK_SDIO0:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
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SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
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@@ -662,6 +668,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
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case HCLK_EMMC:
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case HCLK_SDMMC:
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case HCLK_SDIO0:
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+ case SCLK_EMMC:
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+ case SCLK_SDMMC:
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+ case SCLK_SDIO0:
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new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
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break;
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case SCLK_SPI0:
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@@ -706,6 +715,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
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case HCLK_EMMC:
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case HCLK_SDMMC:
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case HCLK_SDIO0:
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+ case SCLK_EMMC:
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+ case SCLK_SDMMC:
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+ case SCLK_SDIO0:
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new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
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break;
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case SCLK_SPI0:
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