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@@ -0,0 +1,142 @@
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+/*
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+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <dm/device.h>
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+#include <dm/pinctrl.h>
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+#include <libfdt.h>
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+#include <asm/io.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+struct single_pdata {
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+ fdt_addr_t base; /* first configuration register */
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+ int offset; /* index of last configuration register */
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+ u32 mask; /* configuration-value mask bits */
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+ int width; /* configuration register bit width */
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+};
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+
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+struct single_fdt_pin_cfg {
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+ fdt32_t reg; /* configuration register offset */
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+ fdt32_t val; /* configuration register value */
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+};
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+
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+/**
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+ * single_configure_pins() - Configure pins based on FDT data
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+ *
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+ * @dev: Pointer to single pin configuration device which is the parent of
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+ * the pins node holding the pin configuration data.
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+ * @pins: Pointer to the first element of an array of register/value pairs
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+ * of type 'struct single_fdt_pin_cfg'. Each such pair describes the
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+ * the pin to be configured and the value to be used for configuration.
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+ * This pointer points to a 'pinctrl-single,pins' property in the
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+ * device-tree.
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+ * @size: Size of the 'pins' array in bytes.
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+ * The number of register/value pairs in the 'pins' array therefore
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+ * equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
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+ */
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+static int single_configure_pins(struct udevice *dev,
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+ const struct single_fdt_pin_cfg *pins,
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+ int size)
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+{
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+ struct single_pdata *pdata = dev->platdata;
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+ int count = size / sizeof(struct single_fdt_pin_cfg);
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+ int n, reg;
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+ u32 val;
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+
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+ for (n = 0; n < count; n++) {
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+ reg = fdt32_to_cpu(pins->reg);
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+ if ((reg < 0) || (reg > pdata->offset)) {
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+ dev_dbg(dev, " invalid register offset 0x%08x\n", reg);
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+ pins++;
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+ continue;
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+ }
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+ reg += pdata->base;
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+ switch (pdata->width) {
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+ case 32:
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+ val = readl(reg) & ~pdata->mask;
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+ val |= fdt32_to_cpu(pins->val) & pdata->mask;
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+ writel(val, reg);
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+ dev_dbg(dev, " reg/val 0x%08x/0x%08x\n",
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+ reg, val);
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+ break;
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+ default:
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+ dev_warn(dev, "unsupported register width %i\n",
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+ pdata->width);
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+ }
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+ pins++;
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+ }
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+ return 0;
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+}
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+
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+static int single_set_state(struct udevice *dev,
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+ struct udevice *config)
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+{
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+ const void *fdt = gd->fdt_blob;
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+ const struct single_fdt_pin_cfg *prop;
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+ int len;
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+
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+ prop = fdt_getprop(fdt, config->of_offset, "pinctrl-single,pins", &len);
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+ if (prop) {
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+ dev_dbg(dev, "configuring pins for %s\n", config->name);
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+ if (len % sizeof(struct single_fdt_pin_cfg)) {
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+ dev_dbg(dev, " invalid pin configuration in fdt\n");
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+ return -FDT_ERR_BADSTRUCTURE;
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+ }
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+ single_configure_pins(dev, prop, len);
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+ len = 0;
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+ }
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+
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+ return len;
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+}
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+
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+static int single_ofdata_to_platdata(struct udevice *dev)
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+{
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+ fdt_addr_t addr;
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+ u32 of_reg[2];
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+ int res;
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+ struct single_pdata *pdata = dev->platdata;
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+
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+ pdata->width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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+ "pinctrl-single,register-width", 0);
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+
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+ res = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
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+ "reg", of_reg, 2);
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+ if (res)
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+ return res;
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+ pdata->offset = of_reg[1] - pdata->width / 8;
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+
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+ addr = dev_get_addr(dev);
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+ if (addr == FDT_ADDR_T_NONE) {
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+ dev_dbg(dev, "no valid base register address\n");
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+ return -EINVAL;
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+ }
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+ pdata->base = addr;
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+
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+ pdata->mask = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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+ "pinctrl-single,function-mask",
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+ 0xffffffff);
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+ return 0;
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+}
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+
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+const struct pinctrl_ops single_pinctrl_ops = {
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+ .set_state = single_set_state,
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+};
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+
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+static const struct udevice_id single_pinctrl_match[] = {
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+ { .compatible = "pinctrl-single" },
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+ { /* sentinel */ }
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+};
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+
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+U_BOOT_DRIVER(single_pinctrl) = {
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+ .name = "single-pinctrl",
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+ .id = UCLASS_PINCTRL,
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+ .of_match = single_pinctrl_match,
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+ .ops = &single_pinctrl_ops,
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+ .flags = DM_FLAG_PRE_RELOC,
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+ .platdata_auto_alloc_size = sizeof(struct single_pdata),
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+ .ofdata_to_platdata = single_ofdata_to_platdata,
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+};
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