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arm: mvebu: Fix ddr3_init() cpu config

Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
Dirk Eibach 9 years ago
parent
commit
44876bf9e8
1 changed files with 0 additions and 2 deletions
  1. 0 2
      drivers/ddr/marvell/a38x/ddr3_init.c

+ 0 - 2
drivers/ddr/marvell/a38x/ddr3_init.c

@@ -305,8 +305,6 @@ int ddr3_init(void)
 		SAR1_CPU_CORE_OFFSET;
 		SAR1_CPU_CORE_OFFSET;
 	switch (soc_num) {
 	switch (soc_num) {
 	case 0x3:
 	case 0x3:
-		reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
-		reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
 	case 0x1:
 	case 0x1:
 		reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 		reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 	case 0x0:
 	case 0x0: