tegra: Convert CONFIG_PWM_TEGRA to Kconfig

Move this option to Kconfig and clean up the header files. Adjust the only
user (the LCD driver) to work with the new driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

configs/colibri_t20_defconfig

@@ -14,6 +14,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

configs/harmony_defconfig

@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

configs/medcom-wide_defconfig

@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

configs/nyan-big_defconfig

@@ -26,6 +26,7 @@ CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_TEGRA114_SPI=y
 CONFIG_TPM_TIS_INFINEON=y

configs/paz00_defconfig

@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

configs/seaboard_defconfig

@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

configs/tec_defconfig

@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

configs/ventana_defconfig

@@ -15,6 +15,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_DM_PMIC=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_PWM=y
+CONFIG_PWM_TEGRA=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

drivers/pwm/Kconfig

@@ -17,3 +17,11 @@ config PWM_ROCKCHIP
 	  programmable period and duty cycle. A 32-bit counter is used.
 	  Various options provided in the hardware (such as capture mode and
 	  continuous/single-shot) are not supported by the driver.
+
+config PWM_TEGRA
+	bool "Enable support for the Tegra PWM"
+	help
+	  This PWM is found on Tegra 20 and other Nvidia SoCs. It supports
+	  four channels with a programmable period and duty cycle. Only a
+	  32KHz clock is supported by the driver but the duty cycle is
+	  configurable.

include/configs/colibri_t20.h

@@ -53,7 +53,6 @@
 #define CONFIG_TFTP_TSIZE
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_SYS_WHITE_ON_BLACK
 #define CONFIG_CONSOLE_SCROLL_LINES	10
 #define CONFIG_CMD_BMP

include/configs/harmony.h

@@ -60,7 +60,6 @@
 #define CONFIG_CMD_DHCP
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_SYS_WHITE_ON_BLACK
 #define CONFIG_CONSOLE_SCROLL_LINES	10
 

include/configs/medcom-wide.h

@@ -48,7 +48,6 @@
 #define CONFIG_CMD_DHCP
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* support the new (FDT-based) image format */

include/configs/nyan-big.h

@@ -38,7 +38,6 @@
 #define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_AS3722_POWER
 #define CONFIG_SYS_WHITE_ON_BLACK
 #define CONFIG_CMD_BMP

include/configs/paz00.h

@@ -48,7 +48,6 @@
 #define CONFIG_CMD_DHCP
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_SYS_WHITE_ON_BLACK
 #define CONFIG_CONSOLE_SCROLL_LINES	10
 

include/configs/seaboard.h

@@ -66,7 +66,6 @@
 #define CONFIG_USB_KEYBOARD
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_SYS_WHITE_ON_BLACK
 #define CONFIG_CONSOLE_SCROLL_LINES	10
 

include/configs/tec.h

@@ -48,7 +48,6 @@
 #define CONFIG_CMD_DHCP
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* support the new (FDT-based) image format */

include/configs/ventana.h

@@ -49,7 +49,6 @@
 #define CONFIG_USB_KEYBOARD
 
 /* LCD support */
-#define CONFIG_PWM_TEGRA
 #define CONFIG_SYS_WHITE_ON_BLACK
 #define CONFIG_CONSOLE_SCROLL_LINES	10