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@@ -31,7 +31,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
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u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
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-#if defined CONFIG_MX6SL
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+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
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/* Check whether LVE bit needs to be set */
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if (pad_ctrl & PAD_CTL_LVE) {
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pad_ctrl &= ~PAD_CTL_LVE;
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@@ -51,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
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}
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#else
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- if (is_mx6ull()) {
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+ if (is_mx6ull() || is_mx6sll()) {
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if (lpsr == IOMUX_CONFIG_LPSR) {
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base = (void *)IOMUXC_SNVS_BASE_ADDR;
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mux_mode &= ~IOMUX_CONFIG_LPSR;
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@@ -60,7 +60,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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#endif
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#endif
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- if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs)
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+ if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
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__raw_writel(mux_mode, base + mux_ctrl_ofs);
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if (sel_input_ofs)
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@@ -73,6 +73,10 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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#else
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if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
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__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
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+#if defined(CONFIG_MX6SLL)
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+ else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
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+ clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
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+#endif
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#endif
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#ifdef CONFIG_IOMUX_LPSR
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