rockchip: spl: RK3399: use boot0 hook to create space for SPL magic

The SPL binary needs to be prefixed with the boot magic ('RK33' for
the RK3399) on the Rockchip platform and starts execution of the
instruction word following immediately after this boot magic.

This poses a challenge for AArch64 (ARMv8) binaries, as the .text
section would need to start on the odd address, violating natural
alignment (and potentially triggering a fault for any code that
tries to access 64bit values embedded in the .text section).

A quick and easy fix is to have the .text section include the 'RK33'
magic and pad it with a boot0 hook to insert 4 bytes of padding at the
start of the section (with the intention of having mkimage overwrite
this padding with the appropriate boot magic). This avoids having to
modify the linker scripts or more complex logic in mkimage.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>

arch/arm/include/asm/arch-rockchip/boot0.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK33').
+ *
+ * To make life easier for everyone, we build the SPL binary with
+ * space for this 4-byte header already included in the binary.
+ */
+
+#ifdef CONFIG_SPL_BUILD
+	.space 0x4         /* space for the 'RK33' */
+#endif
+	b reset

arch/arm/mach-rockchip/Kconfig

@@ -54,6 +54,7 @@ config ROCKCHIP_RK3399
 	select SUPPORT_SPL
 	select SPL
 	select SPL_SEPARATE_BSS
+	select ENABLE_ARM_SOC_BOOT0_HOOK
 	help
 	  The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
 	  and quad-core Cortex-A53.

include/configs/rk3399_common.h

@@ -27,7 +27,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0xff8effff
-#define CONFIG_SPL_TEXT_BASE		0xff8c2008
+#define CONFIG_SPL_TEXT_BASE		0xff8c2000
 #define CONFIG_SPL_MAX_SIZE		0x30000
 /*  BSS setup */
 #define CONFIG_SPL_BSS_START_ADDR       0xff8e0000