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@@ -13,24 +13,28 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_SET_REG(fld, val) \
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#define I2C_SET_REG(fld, val) \
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- { if (I2C_ADAP_HWNR & 0x10) \
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- FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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- else \
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- FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
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+ do { \
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+ if (I2C_ADAP_HWNR & 0x10) \
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+ FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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+ else \
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+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
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+ } while (0)
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#else
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#else
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#define I2C_SET_REG(fld, val) \
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#define I2C_SET_REG(fld, val) \
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- FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
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+ FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_GET_REG(fld, val) \
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#define I2C_GET_REG(fld, val) \
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- { if (I2C_ADAP_HWNR & 0x10) \
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- FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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- else \
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- FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
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+ do { \
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+ if (I2C_ADAP_HWNR & 0x10) \
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+ FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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+ else \
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+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
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+ } while (0)
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#else
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#else
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#define I2C_GET_REG(fld, val) \
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#define I2C_GET_REG(fld, val) \
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- FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
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+ FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
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#endif
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#endif
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enum {
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enum {
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