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@@ -3,6 +3,24 @@ if ARM64
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config ARMV8_MULTIENTRY
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bool "Enable multiple CPUs to enter into U-Boot"
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+config ARMV8_SET_SMPEN
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+ bool "Enable data coherency with other cores in cluster"
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+ help
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+ Say Y here if there is not any trust firmware to set
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+ CPUECTLR_EL1.SMPEN bit before U-Boot.
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+
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+ For A53, it enables data coherency with other cores in the
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+ cluster, and for A57/A72, it enables receiving of instruction
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+ cache and TLB maintenance operations.
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+ Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
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+ for single core systems. Unfortunately write access to this
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+ register may be controlled by EL3/EL2 firmware. To be more
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+ precise, by default (if there is EL2/EL3 firmware running)
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+ this register is RO for NS EL1.
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+ This switch can be used to avoid writing to CPUECTLR_EL1,
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+ it can be safely enabled when EL2/EL3 initialized SMPEN bit
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+ or when CPU implementation doesn't include that register.
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+
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config ARMV8_SPIN_TABLE
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bool "Support spin-table enable method"
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depends on ARMV8_MULTIENTRY && OF_LIBFDT
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