fsl-ddr: Fix the chip-select interleaving issue

commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3
introduced one new bug to chip-select interleaving.

Single DDR controller also can do the chip-select
interleaving if there is dual-rank or qual-rank DIMMs.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

cpu/mpc8xxx/ddr/options.c

@@ -22,9 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			unsigned int ctrl_num)
 {
 	unsigned int i;
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	const char *p;
-#endif
 
 	/* Chip select options. */
 
@@ -242,8 +240,10 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 						simple_strtoul(p, NULL, 0);
 		}
 	}
+#endif
 
-	if( (p = getenv("ba_intlv_ctl")) != NULL) {
+	if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
+		(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 		if (strcmp(p, "cs0_cs1") == 0)
 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 		else if (strcmp(p, "cs2_cs3") == 0)
@@ -283,7 +283,6 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			break;
 		}
 	}
-#endif
 
 	fsl_ddr_board_options(popts, pdimm, ctrl_num);