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@@ -81,14 +81,6 @@ reset:
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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- /* Enalbe SMPEN bit for coherency.
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- * This register is not architectural but at the moment
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- * this bit should be set for A53/A57/A72.
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- */
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- mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
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- orr x0, x0, #0x40
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- msr S3_1_c15_c2_1, x0
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-
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/* Apply ARM core specific erratas */
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bl apply_core_errata
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