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@@ -18,7 +18,6 @@
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_START_EN (0x1)
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#define VTP_CTRL_START_EN (0x1)
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-#define PHY_DLL_LOCK_DIFF 0x0
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#define DDR_CKE_CTRL_NORMAL 0x1
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#define DDR_CKE_CTRL_NORMAL 0x1
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#define PHY_EN_DYN_PWRDN (0x1 << 20)
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#define PHY_EN_DYN_PWRDN (0x1 << 20)
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@@ -29,7 +28,6 @@
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#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
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#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
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#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
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#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
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#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
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#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
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-#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
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#define MT47H128M16RT25E_RATIO 0x80
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#define MT47H128M16RT25E_RATIO 0x80
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#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
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#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
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#define MT47H128M16RT25E_RD_DQS 0x12
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#define MT47H128M16RT25E_RD_DQS 0x12
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@@ -38,7 +36,6 @@
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#define MT47H128M16RT25E_PHY_GATELVL 0x00
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#define MT47H128M16RT25E_PHY_GATELVL 0x00
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#define MT47H128M16RT25E_PHY_WR_DATA 0x40
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#define MT47H128M16RT25E_PHY_WR_DATA 0x40
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#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
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#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
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-#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
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#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
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#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
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/* Micron MT41J128M16JT-125 */
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/* Micron MT41J128M16JT-125 */
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@@ -49,7 +46,6 @@
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#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
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#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
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#define MT41J128MJT125_EMIF_SDREF 0x0000093B
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#define MT41J128MJT125_EMIF_SDREF 0x0000093B
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#define MT41J128MJT125_ZQ_CFG 0x50074BE4
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#define MT41J128MJT125_ZQ_CFG 0x50074BE4
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-#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
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#define MT41J128MJT125_RATIO 0x40
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#define MT41J128MJT125_RATIO 0x40
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#define MT41J128MJT125_INVERT_CLKOUT 0x1
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#define MT41J128MJT125_INVERT_CLKOUT 0x1
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#define MT41J128MJT125_RD_DQS 0x3B
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#define MT41J128MJT125_RD_DQS 0x3B
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@@ -72,7 +68,6 @@
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#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
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#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
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#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
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#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
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#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
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#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
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-#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
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#define MT41J256M8HX15E_RATIO 0x40
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#define MT41J256M8HX15E_RATIO 0x40
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#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
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#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
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#define MT41J256M8HX15E_RD_DQS 0x3B
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#define MT41J256M8HX15E_RD_DQS 0x3B
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@@ -89,7 +84,6 @@
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
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#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
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#define MT41K256M16HA125E_EMIF_SDREF 0xC30
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#define MT41K256M16HA125E_EMIF_SDREF 0xC30
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#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
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#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
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-#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
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#define MT41K256M16HA125E_RATIO 0x80
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#define MT41K256M16HA125E_RATIO 0x80
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#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
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#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
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#define MT41K256M16HA125E_RD_DQS 0x38
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#define MT41K256M16HA125E_RD_DQS 0x38
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@@ -106,7 +100,6 @@
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#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
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#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
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#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
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#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
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#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
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#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
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-#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
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#define MT41J512M8RH125_RATIO 0x80
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#define MT41J512M8RH125_RATIO 0x80
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#define MT41J512M8RH125_INVERT_CLKOUT 0x0
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#define MT41J512M8RH125_INVERT_CLKOUT 0x0
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#define MT41J512M8RH125_RD_DQS 0x3B
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#define MT41J512M8RH125_RD_DQS 0x3B
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@@ -123,7 +116,6 @@
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#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
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#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
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#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
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#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
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#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
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#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
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-#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
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#define K4B2G1646EBIH9_RATIO 0x80
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#define K4B2G1646EBIH9_RATIO 0x80
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#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
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#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
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#define K4B2G1646EBIH9_RD_DQS 0x35
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#define K4B2G1646EBIH9_RD_DQS 0x35
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@@ -155,18 +147,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr);
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struct ddr_cmd_regs {
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struct ddr_cmd_regs {
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unsigned int resv0[7];
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unsigned int resv0[7];
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unsigned int cm0csratio; /* offset 0x01C */
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unsigned int cm0csratio; /* offset 0x01C */
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- unsigned int resv1[2];
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- unsigned int cm0dldiff; /* offset 0x028 */
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+ unsigned int resv1[3];
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int resv2[8];
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unsigned int resv2[8];
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unsigned int cm1csratio; /* offset 0x050 */
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unsigned int cm1csratio; /* offset 0x050 */
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- unsigned int resv3[2];
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- unsigned int cm1dldiff; /* offset 0x05C */
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+ unsigned int resv3[3];
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int resv4[8];
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unsigned int resv4[8];
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unsigned int cm2csratio; /* offset 0x084 */
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unsigned int cm2csratio; /* offset 0x084 */
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- unsigned int resv5[2];
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- unsigned int cm2dldiff; /* offset 0x090 */
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+ unsigned int resv5[3];
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int resv6[3];
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unsigned int resv6[3];
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};
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};
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@@ -203,24 +192,21 @@ struct ddr_regs {
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unsigned int cm0configclk; /* offset 0x010 */
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unsigned int cm0configclk; /* offset 0x010 */
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unsigned int resv1[2];
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unsigned int resv1[2];
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unsigned int cm0csratio; /* offset 0x01C */
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unsigned int cm0csratio; /* offset 0x01C */
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- unsigned int resv2[2];
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- unsigned int cm0dldiff; /* offset 0x028 */
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+ unsigned int resv2[3];
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int resv3[4];
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unsigned int resv3[4];
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unsigned int cm1config; /* offset 0x040 */
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unsigned int cm1config; /* offset 0x040 */
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unsigned int cm1configclk; /* offset 0x044 */
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unsigned int cm1configclk; /* offset 0x044 */
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unsigned int resv4[2];
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unsigned int resv4[2];
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unsigned int cm1csratio; /* offset 0x050 */
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unsigned int cm1csratio; /* offset 0x050 */
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- unsigned int resv5[2];
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- unsigned int cm1dldiff; /* offset 0x05C */
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+ unsigned int resv5[3];
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int resv6[4];
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unsigned int resv6[4];
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unsigned int cm2config; /* offset 0x074 */
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unsigned int cm2config; /* offset 0x074 */
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unsigned int cm2configclk; /* offset 0x078 */
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unsigned int cm2configclk; /* offset 0x078 */
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unsigned int resv7[2];
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unsigned int resv7[2];
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unsigned int cm2csratio; /* offset 0x084 */
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unsigned int cm2csratio; /* offset 0x084 */
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- unsigned int resv8[2];
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- unsigned int cm2dldiff; /* offset 0x090 */
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+ unsigned int resv8[3];
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int resv9[12];
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unsigned int resv9[12];
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unsigned int dt0rdsratio0; /* offset 0x0C8 */
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unsigned int dt0rdsratio0; /* offset 0x0C8 */
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@@ -249,17 +235,14 @@ struct cmd_control {
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unsigned long cmd0csratio;
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unsigned long cmd0csratio;
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unsigned long cmd0csforce;
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unsigned long cmd0csforce;
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unsigned long cmd0csdelay;
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unsigned long cmd0csdelay;
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- unsigned long cmd0dldiff;
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unsigned long cmd0iclkout;
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unsigned long cmd0iclkout;
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unsigned long cmd1csratio;
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unsigned long cmd1csratio;
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unsigned long cmd1csforce;
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unsigned long cmd1csforce;
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unsigned long cmd1csdelay;
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unsigned long cmd1csdelay;
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- unsigned long cmd1dldiff;
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unsigned long cmd1iclkout;
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unsigned long cmd1iclkout;
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unsigned long cmd2csratio;
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unsigned long cmd2csratio;
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unsigned long cmd2csforce;
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unsigned long cmd2csforce;
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unsigned long cmd2csdelay;
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unsigned long cmd2csdelay;
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- unsigned long cmd2dldiff;
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unsigned long cmd2iclkout;
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unsigned long cmd2iclkout;
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};
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};
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@@ -273,8 +256,6 @@ struct ddr_data {
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unsigned long datagiratio0;
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unsigned long datagiratio0;
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unsigned long datafwsratio0;
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unsigned long datafwsratio0;
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unsigned long datawrsratio0;
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unsigned long datawrsratio0;
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- unsigned long datauserank0delay;
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- unsigned long datadldiff0;
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};
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};
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/**
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/**
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