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@@ -1220,6 +1220,20 @@ void enable_thermal_clk(void)
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enable_pll3();
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}
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+#ifdef CONFIG_MTD_NOR_FLASH
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+void enable_eim_clk(unsigned char enable)
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+{
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+ u32 reg;
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+
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+ reg = __raw_readl(&imx_ccm->CCGR6);
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+ if (enable)
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+ reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
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+ else
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+ reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
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+ __raw_writel(reg, &imx_ccm->CCGR6);
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+}
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+#endif
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+
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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@@ -1262,6 +1276,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
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return 0;
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}
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+#ifndef CONFIG_SPL_BUILD
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/*
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* Dump some core clockes.
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*/
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@@ -1463,20 +1478,6 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
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}
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#endif
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-#ifdef CONFIG_MTD_NOR_FLASH
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-void enable_eim_clk(unsigned char enable)
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-{
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- u32 reg;
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-
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- reg = __raw_readl(&imx_ccm->CCGR6);
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- if (enable)
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- reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
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- else
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- reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
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- __raw_writel(reg, &imx_ccm->CCGR6);
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-}
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-#endif
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-
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/***************************************************/
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U_BOOT_CMD(
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@@ -1484,3 +1485,4 @@ U_BOOT_CMD(
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"display clocks",
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""
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);
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+#endif
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