|
@@ -16,6 +16,8 @@
|
|
#include <asm/arch/prcm.h>
|
|
#include <asm/arch/prcm.h>
|
|
#include <asm/arch/rsb.h>
|
|
#include <asm/arch/rsb.h>
|
|
|
|
|
|
|
|
+static int rsb_set_device_mode(void);
|
|
|
|
+
|
|
static void rsb_cfg_io(void)
|
|
static void rsb_cfg_io(void)
|
|
{
|
|
{
|
|
#ifdef CONFIG_MACH_SUN8I
|
|
#ifdef CONFIG_MACH_SUN8I
|
|
@@ -53,7 +55,7 @@ static void rsb_set_clk(void)
|
|
writel((cd_odly << 8) | div, &rsb->ccr);
|
|
writel((cd_odly << 8) | div, &rsb->ccr);
|
|
}
|
|
}
|
|
|
|
|
|
-void rsb_init(void)
|
|
|
|
|
|
+int rsb_init(void)
|
|
{
|
|
{
|
|
struct sunxi_rsb_reg * const rsb =
|
|
struct sunxi_rsb_reg * const rsb =
|
|
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
|
|
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
|
|
@@ -65,6 +67,8 @@ void rsb_init(void)
|
|
|
|
|
|
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
|
|
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
|
|
rsb_set_clk();
|
|
rsb_set_clk();
|
|
|
|
+
|
|
|
|
+ return rsb_set_device_mode();
|
|
}
|
|
}
|
|
|
|
|
|
static int rsb_await_trans(void)
|
|
static int rsb_await_trans(void)
|
|
@@ -99,13 +103,14 @@ static int rsb_await_trans(void)
|
|
return ret;
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
|
|
-int rsb_set_device_mode(u32 device_mode_data)
|
|
|
|
|
|
+static int rsb_set_device_mode(void)
|
|
{
|
|
{
|
|
struct sunxi_rsb_reg * const rsb =
|
|
struct sunxi_rsb_reg * const rsb =
|
|
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
|
|
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
|
|
unsigned long tmo = timer_get_us() + 1000000;
|
|
unsigned long tmo = timer_get_us() + 1000000;
|
|
|
|
|
|
- writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
|
|
|
|
|
|
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
|
|
|
|
+ &rsb->dmcr);
|
|
|
|
|
|
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
|
|
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
|
|
if (timer_get_us() > tmo)
|
|
if (timer_get_us() > tmo)
|