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@@ -12,6 +12,8 @@
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/dma.h>
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#include <asm/imx-common/dma.h>
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#include <asm/imx-common/hab.h>
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#include <asm/imx-common/hab.h>
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+#include <asm/imx-common/rdc-sema.h>
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+#include <asm/arch/imx-rdc.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/crm_regs.h>
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#include <dm.h>
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#include <dm.h>
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#include <imx_thermal.h>
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#include <imx_thermal.h>
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@@ -29,6 +31,65 @@ U_BOOT_DEVICE(imx7_thermal) = {
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};
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};
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#endif
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#endif
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+#ifdef CONFIG_IMX_RDC
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+/*
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+ * In current design, if any peripheral was assigned to both A7 and M4,
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+ * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
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+ * low power mode. So M4 sleep will cause some peripherals fail to work
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+ * at A7 core side. At default, all resources are in domain 0 - 3.
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+ *
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+ * There are 26 peripherals impacted by this IC issue:
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+ * SIM2(sim2/emvsim2)
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+ * SIM1(sim1/emvsim1)
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+ * UART1/UART2/UART3/UART4/UART5/UART6/UART7
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+ * SAI1/SAI2/SAI3
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+ * WDOG1/WDOG2/WDOG3/WDOG4
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+ * GPT1/GPT2/GPT3/GPT4
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+ * PWM1/PWM2/PWM3/PWM4
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+ * ENET1/ENET2
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+ * Software Workaround:
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+ * Here we setup some resources to domain 0 where M4 codes will move
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+ * the M4 out of this domain. Then M4 is not able to access them any longer.
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+ * This is a workaround for ic issue. So the peripherals are not shared
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+ * by them. This way requires the uboot implemented the RDC driver and
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+ * set the 26 IPs above to domain 0 only. M4 code will assign resource
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+ * to its own domain, if it want to use the resource.
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+ */
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+static rdc_peri_cfg_t const resources[] = {
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+ (RDC_PER_SIM1 | RDC_DOMAIN(0)),
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+ (RDC_PER_SIM2 | RDC_DOMAIN(0)),
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+ (RDC_PER_UART1 | RDC_DOMAIN(0)),
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+ (RDC_PER_UART2 | RDC_DOMAIN(0)),
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+ (RDC_PER_UART3 | RDC_DOMAIN(0)),
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+ (RDC_PER_UART4 | RDC_DOMAIN(0)),
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+ (RDC_PER_UART5 | RDC_DOMAIN(0)),
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+ (RDC_PER_UART6 | RDC_DOMAIN(0)),
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+ (RDC_PER_UART7 | RDC_DOMAIN(0)),
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+ (RDC_PER_SAI1 | RDC_DOMAIN(0)),
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+ (RDC_PER_SAI2 | RDC_DOMAIN(0)),
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+ (RDC_PER_SAI3 | RDC_DOMAIN(0)),
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+ (RDC_PER_WDOG1 | RDC_DOMAIN(0)),
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+ (RDC_PER_WDOG2 | RDC_DOMAIN(0)),
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+ (RDC_PER_WDOG3 | RDC_DOMAIN(0)),
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+ (RDC_PER_WDOG4 | RDC_DOMAIN(0)),
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+ (RDC_PER_GPT1 | RDC_DOMAIN(0)),
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+ (RDC_PER_GPT2 | RDC_DOMAIN(0)),
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+ (RDC_PER_GPT3 | RDC_DOMAIN(0)),
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+ (RDC_PER_GPT4 | RDC_DOMAIN(0)),
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+ (RDC_PER_PWM1 | RDC_DOMAIN(0)),
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+ (RDC_PER_PWM2 | RDC_DOMAIN(0)),
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+ (RDC_PER_PWM3 | RDC_DOMAIN(0)),
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+ (RDC_PER_PWM4 | RDC_DOMAIN(0)),
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+ (RDC_PER_ENET1 | RDC_DOMAIN(0)),
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+ (RDC_PER_ENET2 | RDC_DOMAIN(0)),
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+};
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+
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+static void isolate_resource(void)
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+{
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+ imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
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+}
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+#endif
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+
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#if defined(CONFIG_SECURE_BOOT)
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#if defined(CONFIG_SECURE_BOOT)
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struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
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struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
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.bank = 1,
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.bank = 1,
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@@ -163,6 +224,9 @@ int arch_cpu_init(void)
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mxs_dma_init();
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mxs_dma_init();
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#endif
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#endif
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+ if (IS_ENABLED(CONFIG_IMX_RDC))
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+ isolate_resource();
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+
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return 0;
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return 0;
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}
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}
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