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@@ -118,6 +118,23 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
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}
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}
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+#ifdef CONFIG_MACH_SUN8I_R40
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+/* secondary core entry address is programmed differently on R40 */
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+static void __secure sunxi_set_entry_address(void *entry)
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+{
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+ writel((u32)entry,
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+ SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
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+}
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+#else
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+static void __secure sunxi_set_entry_address(void *entry)
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+{
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+ struct sunxi_cpucfg_reg *cpucfg =
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+ (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
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+
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+ writel((u32)entry, &cpucfg->priv0);
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+}
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+#endif
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+
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#ifdef CONFIG_MACH_SUN7I
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/* sun7i (A20) is different from other single cluster SoCs */
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static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
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@@ -236,13 +253,7 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc)
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psci_save_target_pc(cpu, pc);
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/* Set secondary core power on PC */
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-#ifdef CONFIG_MACH_SUN8I_R40
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- /* secondary core entry address is programmed differently */
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- writel((u32)&psci_cpu_entry,
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- SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
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-#else
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- writel((u32)&psci_cpu_entry, &cpucfg->priv0);
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-#endif
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+ sunxi_set_entry_address(&psci_cpu_entry);
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/* Assert reset on target CPU */
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writel(0, &cpucfg->cpu[cpu].rst);
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