Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

arch/arm/dts/socfpga_arria5_socdk.dts

@@ -25,6 +25,7 @@
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
+		udc0 = &usb1;
 	};
 
 	regulator_3_3v: 3-3-v-regulator {

arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts

@@ -16,6 +16,7 @@
 
 	aliases {
 		ethernet0 = &gmac1;
+		udc0 = &usb1;
 	};
 
 	memory {
@@ -59,3 +60,7 @@
 	status = "okay";
 	u-boot,dm-pre-reloc;
 };
+
+&usb1 {
+	status = "okay";
+};

arch/arm/dts/socfpga_cyclone5_mcvevk.dts

@@ -16,6 +16,7 @@
 
 	aliases {
 		ethernet0 = &gmac0;
+		udc0 = &usb1;
 	};
 
 	memory {
@@ -51,3 +52,7 @@
 	bus-width = <8>;
 	u-boot,dm-pre-reloc;
 };
+
+&usb1 {
+	status = "okay";
+};

arch/arm/dts/socfpga_cyclone5_socdk.dts

@@ -25,6 +25,7 @@
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
+		udc0 = &usb1;
 	};
 
 	regulator_3_3v: 3-3-v-regulator {
@@ -77,10 +78,6 @@
 	vqmmc-supply = <&regulator_3_3v>;
 };
 
-&usb1 {
-	status = "okay";
-};
-
 &qspi {
 	status = "okay";
 
@@ -100,3 +97,7 @@
 		tslch-ns = <4>;
 	};
 };
+
+&usb1 {
+	status = "okay";
+};

arch/arm/dts/socfpga_cyclone5_sockit.dts

@@ -14,9 +14,10 @@
 		bootargs = "console=ttyS0,115200";
 	};
 
- 	aliases {
+	aliases {
 		ethernet0 = &gmac1;
- 	};
+		udc0 = &usb1;
+	};
 
 	memory {
 		name = "memory";
@@ -90,3 +91,7 @@
 		tslch-ns = <4>;
 	};
 };
+
+&usb1 {
+	status = "okay";
+};

arch/arm/dts/socfpga_cyclone5_socrates.dts

@@ -14,6 +14,10 @@
 		bootargs = "console=ttyS0,115200";
 	};
 
+	aliases {
+		udc0 = &usb1;
+	};
+
 	memory {
 		name = "memory";
 		device_type = "memory";
@@ -28,6 +32,15 @@
 &gmac1 {
 	status = "okay";
 	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
 };
 
 &i2c0 {
@@ -63,3 +76,7 @@
 		tslch-ns = <4>;
 	};
 };
+
+&usb1 {
+	status = "okay";
+};

arch/arm/mach-socfpga/Kconfig

@@ -2,9 +2,14 @@ if ARCH_SOCFPGA
 
 config TARGET_SOCFPGA_ARRIA5
 	bool
+	select TARGET_SOCFPGA_GEN5
 
 config TARGET_SOCFPGA_CYCLONE5
 	bool
+	select TARGET_SOCFPGA_GEN5
+
+config TARGET_SOCFPGA_GEN5
+	bool
 
 choice
 	prompt "Altera SOCFPGA board select"

arch/arm/mach-socfpga/Makefile

@@ -8,11 +8,12 @@
 #
 
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-	   fpga_manager.o scan_manager.o
+	   fpga_manager.o board.o
+
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
-obj-y	+= wrap_pll_config.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5)	+= scan_manager.o wrap_pll_config.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o	\
 			   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)

arch/arm/mach-socfpga/board.c

@@ -0,0 +1,64 @@
+/*
+ * Altera SoCFPGA common board code
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+struct dwc2_plat_otg_data socfpga_otg_data = {
+	.usb_gusbcfg	= 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node[2], count;
+	fdt_addr_t addr;
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
+					   COMPAT_ALTERA_SOCFPGA_DWC2USB,
+					   node, 2);
+	if (count <= 0)	/* No controller found. */
+		return 0;
+
+	addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
+	if (addr == FDT_ADDR_T_NONE) {
+		printf("UDC Controller has no 'reg' property!\n");
+		return -EINVAL;
+	}
+
+	/* Patch the address from OF into the controller pdata. */
+	socfpga_otg_data.regs_otg = addr;
+
+	return dwc2_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+	return 1;
+}
+#endif

arch/arm/mach-socfpga/include/mach/system_manager.h

@@ -129,9 +129,13 @@ struct socfpga_system_manager {
 #define SYSMGR_FPGAINTF_NAND	(1 << 4)
 #define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
 
-/* FIXME: This is questionable macro. */
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
-	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	3
+#else
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#endif
+
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
 
 /* EMAC Group Bit definitions */
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0

board/altera/arria5-socdk/socfpga.c

@@ -3,83 +3,4 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
-	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
-	.usb_gusbcfg	= 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
-	return 1;
-}
-#endif

board/altera/cyclone5-socdk/socfpga.c

@@ -3,83 +3,4 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
-	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
-	.usb_gusbcfg	= 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
-	return 1;
-}
-#endif

board/denx/mcvevk/socfpga.c

@@ -3,43 +3,4 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
-	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
-	.usb_gusbcfg	= 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
-	return 1;
-}
-#endif

board/ebv/socrates/socfpga.c

@@ -3,83 +3,4 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
-	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
-	.usb_gusbcfg	= 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
-	return 1;
-}
-#endif

board/sr1500/socfpga.c

@@ -5,27 +5,10 @@
  */
 
 #include <common.h>
-#include <i2c.h>
-#include <miiphy.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
 int board_early_init_f(void)
 {
 	int ret;

board/terasic/de0-nano-soc/socfpga.c

@@ -3,70 +3,4 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <common.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9031
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0x70);
-	if (ret)
-		return ret;
-
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0x7777);
-	if (ret)
-		return ret;
-
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0);
-	if (ret)
-		return ret;
-
-	ret = ksz9031_phy_extended_write(phydev, 0x2,
-					 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
-					 MII_KSZ9031_MOD_DATA_NO_POST_INC,
-					 0x03FC);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif

board/terasic/sockit/socfpga.c

@@ -3,83 +3,4 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
 #include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
-	/* Address of boot parameters for ATAG (if ATAG is used) */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
-	int ret;
-	/*
-	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
-	 * to work reliably on most flavors of cyclone5 boards.
-	 */
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					 0x0);
-	if (ret)
-		return ret;
-
-	ret = ksz9021_phy_extended_write(phydev,
-					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					 0xf0f0);
-	if (ret)
-		return ret;
-
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct dwc2_plat_otg_data socfpga_otg_data = {
-	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
-	.usb_gusbcfg	= 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	return dwc2_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
-	return 1;
-}
-#endif

configs/socfpga_arria5_defconfig

@@ -21,3 +21,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/socfpga_cyclone5_defconfig

@@ -21,3 +21,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/socfpga_de0_nano_soc_defconfig

@@ -19,3 +19,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/socfpga_mcvevk_defconfig

@@ -19,3 +19,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/socfpga_sockit_defconfig

@@ -23,3 +23,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/socfpga_socrates_defconfig

@@ -22,3 +22,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

drivers/mmc/socfpga_dw_mmc.c

@@ -33,6 +33,8 @@ struct dwmci_socfpga_priv_data {
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
 	struct dwmci_socfpga_priv_data *priv = host->priv;
+	u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
+			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
 	/* Disable SDMMC clock. */
 	clrbits_le32(&clock_manager_base->per_pll.en,
@@ -40,8 +42,7 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
 	debug("%s: drvsel %d smplsel %d\n", __func__,
 	      priv->drvsel, priv->smplsel);
-	writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
-		&system_manager_base->sdmmcgrp_ctrl);
+	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
 		readl(&system_manager_base->sdmmcgrp_ctrl));

drivers/net/phy/micrel.c

@@ -9,9 +9,14 @@
  */
 #include <config.h>
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
 #include <micrel.h>
 #include <phy.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static struct phy_driver KSZ804_driver = {
 	.name = "Micrel KSZ804",
 	.uid = 0x221510,
@@ -174,6 +179,73 @@ static int ksz90xx_startup(struct phy_device *phydev)
 	return 0;
 }
 
+/* Common OF config bits for KSZ9021 and KSZ9031 */
+#if defined(CONFIG_PHY_MICREL_KSZ9021) || defined(CONFIG_PHY_MICREL_KSZ9031)
+#ifdef CONFIG_DM_ETH
+struct ksz90x1_reg_field {
+	const char	*name;
+	const u8	size;	/* Size of the bitfield, in bits */
+	const u8	off;	/* Offset from bit 0 */
+	const u8	dflt;	/* Default value */
+};
+
+struct ksz90x1_ofcfg {
+	const u16			reg;
+	const u16			devad;
+	const struct ksz90x1_reg_field	*grp;
+	const u16			grpsz;
+};
+
+static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
+	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
+	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
+};
+
+static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
+	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
+	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz90x1_of_config_group(struct phy_device *phydev,
+				   struct ksz90x1_ofcfg *ofcfg)
+{
+	struct udevice *dev = phydev->dev;
+	struct phy_driver *drv = phydev->drv;
+	const int ps_to_regval = 200;
+	int val[4];
+	int i, changed = 0, offset, max;
+	u16 regval = 0;
+
+	if (!drv || !drv->writeext)
+		return -EOPNOTSUPP;
+
+	for (i = 0; i < ofcfg->grpsz; i++) {
+		val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+					 ofcfg->grp[i].name, -1);
+		offset = ofcfg->grp[i].off;
+		if (val[i] == -1) {
+			/* Default register value for KSZ9021 */
+			regval |= ofcfg->grp[i].dflt << offset;
+		} else {
+			changed = 1;	/* Value was changed in OF */
+			/* Calculate the register value and fix corner cases */
+			if (val[i] > ps_to_regval * 0xf) {
+				max = (1 << ofcfg->grp[i].size) - 1;
+				regval |= max << offset;
+			} else {
+				regval |= (val[i] / ps_to_regval) << offset;
+			}
+		}
+	}
+
+	if (!changed)
+		return 0;
+
+	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
+}
+#endif
+#endif
+
 #ifdef CONFIG_PHY_MICREL_KSZ9021
 /*
  * KSZ9021
@@ -188,6 +260,35 @@ static int ksz90xx_startup(struct phy_device *phydev)
 #define CTRL1000_CONFIG_MASTER		(1 << 11)
 #define CTRL1000_MANUAL_CONFIG		(1 << 12)
 
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
+	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
+	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
+};
+
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+	struct ksz90x1_ofcfg ofcfg[] = {
+		{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
+		{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
+		{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
+	};
+	int i, ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+		if (ret)
+			return ret;
+
+	return 0;
+}
+#else
+static int ksz9021_of_config(struct phy_device *phydev)
+{
+	return 0;
+}
+#endif
+
 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
 {
 	/* extended registers */
@@ -224,6 +325,11 @@ static int ksz9021_config(struct phy_device *phydev)
 	const unsigned master = CTRL1000_PREFER_MASTER |
 			CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
 	unsigned features = phydev->drv->features;
+	int ret;
+
+	ret = ksz9021_of_config(phydev);
+	if (ret)
+		return ret;
 
 	if (getenv("disable_giga"))
 		features &= ~(SUPPORTED_1000baseT_Half |
@@ -260,6 +366,36 @@ static struct phy_driver ksz9021_driver = {
 #define MII_KSZ9031_MMD_ACCES_CTRL	0x0d
 #define MII_KSZ9031_MMD_REG_DATA	0x0e
 
+#ifdef CONFIG_DM_ETH
+static const struct ksz90x1_reg_field ksz9031_ctl_grp[] =
+	{ { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 } };
+static const struct ksz90x1_reg_field ksz9031_clk_grp[] =
+	{ { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf } };
+
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+	struct ksz90x1_ofcfg ofcfg[] = {
+		{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
+		{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
+		{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
+		{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
+	};
+	int i, ret = 0;
+
+	for (i = 0; i < ARRAY_SIZE(ofcfg); i++)
+		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
+		if (ret)
+			return ret;
+
+	return 0;
+}
+#else
+static int ksz9031_of_config(struct phy_device *phydev)
+{
+	return 0;
+}
+#endif
+
 /* Accessors to extended registers*/
 int ksz9031_phy_extended_write(struct phy_device *phydev,
 			       int devaddr, int regnum, u16 mode, u16 val)
@@ -304,13 +440,21 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
 					 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
 };
 
+static int ksz9031_config(struct phy_device *phydev)
+{
+	int ret;
+	ret = ksz9031_of_config(phydev);
+	if (ret)
+		return ret;
+	return genphy_config(phydev);
+}
 
 static struct phy_driver ksz9031_driver = {
 	.name = "Micrel ksz9031",
 	.uid  = 0x221620,
 	.mask = 0xfffff0,
 	.features = PHY_GBIT_FEATURES,
-	.config   = &genphy_config,
+	.config   = &ksz9031_config,
 	.startup  = &ksz90xx_startup,
 	.shutdown = &genphy_shutdown,
 	.writeext = &ksz9031_phy_extwrite,

include/configs/socfpga_arria5_socdk.h

@@ -47,30 +47,15 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
 #define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER      "Altera"
-
 /* Extra Environment */
-#define CONFIG_HOSTNAME		socfpga_arria5
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

include/configs/socfpga_common.h

@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
+#ifndef __CONFIG_SOCFPGA_COMMON_H__
+#define __CONFIG_SOCFPGA_COMMON_H__
 
 
 /* Virtual target or real hardware */
@@ -69,6 +69,10 @@
 #define CONFIG_CMDLINE_EDITING			/* Command history etc */
 #define CONFIG_SYS_HUSH_PARSER
 
+#ifndef CONFIG_SYS_HOSTNAME
+#define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
+#endif
+
 /*
  * Cache
  */
@@ -229,13 +233,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_DWC2
 #define CONFIG_USB_STORAGE
-/*
- * NOTE: User must define either of the following to select which
- *       of the two USB controllers available on SoCFPGA to use.
- *       The DWC2 driver doesn't support multiple USB controllers.
- * #define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB0_ADDRESS
- * #define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
- */
 #endif
 
 /*
@@ -262,7 +259,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_G_DNL_UMS_VENDOR_NUM	CONFIG_G_DNL_VENDOR_NUM
 #define CONFIG_G_DNL_UMS_PRODUCT_NUM	CONFIG_G_DNL_PRODUCT_NUM
 #ifndef CONFIG_G_DNL_MANUFACTURER
-#define CONFIG_G_DNL_MANUFACTURER	"Altera"
+#define CONFIG_G_DNL_MANUFACTURER	CONFIG_SYS_VENDOR
 #endif
 #endif
 
@@ -326,4 +323,4 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
 
-#endif	/* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
+#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */

include/configs/socfpga_cyclone5_socdk.h

@@ -47,30 +47,15 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
 #define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER      "Altera"
-
 /* Extra Environment */
-#define CONFIG_HOSTNAME		socfpga_cyclone5
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

include/configs/socfpga_de0_nano_soc.h

@@ -37,36 +37,21 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-#else
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9031
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
 #define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER      "Terasic"
-
 /* Extra Environment */
-#define CONFIG_HOSTNAME		socfpga_de0_nano_soc
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \

include/configs/socfpga_mcvevk.h

@@ -48,15 +48,7 @@
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
 #define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER	"DENX"
-
 /* Extra Environment */
-#define CONFIG_HOSTNAME			mcvevk
-
 #define CONFIG_EXTRA_ENV_SETTINGS					\
 	"consdev=ttyS0\0"						\
 	"baudrate=115200\0"						\

include/configs/socfpga_sockit.h

@@ -37,40 +37,21 @@
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND	"run ramboot"
-#else
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
 #define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER      "Terasic"
-
 /* Extra Environment */
-#define CONFIG_HOSTNAME		socfpga_sockit
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

include/configs/socfpga_socrates.h

@@ -43,30 +43,15 @@
 
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)
-
-/* PHY */
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
-#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
-#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
-#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
-#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0
-
 #endif
 
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
 #define CONFIG_ENV_OFFSET		512	/* just after the MBR */
 
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
-#endif
-#define CONFIG_G_DNL_MANUFACTURER      "EBV"
-
 /* Extra Environment */
-#define CONFIG_HOSTNAME		socfpga_socrates
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

include/configs/socfpga_sr1500.h

@@ -53,9 +53,6 @@
 #define CONFIG_PHY_MARVELL
 #define PHY_ANEG_TIMEOUT	8000
 
-/* Extra Environment */
-#define CONFIG_HOSTNAME		sr1500
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

include/fdtdec.h

@@ -167,6 +167,7 @@ enum fdt_compat_id {
 	COMPAT_INTEL_IRQ_ROUTER,	/* Intel Interrupt Router */
 	COMPAT_ALTERA_SOCFPGA_DWMAC,	/* SoCFPGA Ethernet controller */
 	COMPAT_ALTERA_SOCFPGA_DWMMC,	/* SoCFPGA DWMMC controller */
+	COMPAT_ALTERA_SOCFPGA_DWC2USB,	/* SoCFPGA DWC2 USB controller */
 	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 

lib/fdtdec.c

@@ -71,6 +71,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
 	COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
 	COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
+	COMPAT(ALTERA_SOCFPGA_DWC2USB, "snps,dwc2"),
 	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
 	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 };