Merge git://git.denx.de/u-boot-mpc85xx

board/Arcturus/ucp1020/tlb.c

@@ -79,7 +79,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
 		      0, 8, BOOKE_PAGESZ_1G, 1),
 
 #endif /* RAMBOOT/SPL */

board/freescale/b4860qds/tlb.c

@@ -147,7 +147,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 17, BOOKE_PAGESZ_2G, 1)
 #endif
 };

board/freescale/bsc9131rdb/tlb.c

@@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if  defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

board/freescale/bsc9132qds/tlb.c

@@ -71,7 +71,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

board/freescale/c29xpcie/tlb.c

@@ -67,11 +67,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
 			CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_256M, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 9, BOOKE_PAGESZ_256M, 1),
 #endif
 

board/freescale/mpc8541cds/tlb.c

@@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
 	/*

board/freescale/mpc8548cds/tlb.c

@@ -48,7 +48,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
 		      CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 2, BOOKE_PAGESZ_64M, 1),
 
 	/*

board/freescale/mpc8568mds/tlb.c

@@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 
 	/*

board/freescale/p1010rdb/tlb.c

@@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #if defined(CONFIG_SYS_RAMBOOT) || \
 	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

board/freescale/p1022ds/tlb.c

@@ -75,12 +75,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	/* **** - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 8, BOOKE_PAGESZ_1G, 1),
 	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 

board/freescale/p1023rdb/tlb.c

@@ -86,12 +86,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #ifdef CONFIG_SYS_RAMBOOT
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
 		      CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_256M, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_256M, 1),
 #endif
 };

board/freescale/p1_p2_rdb_pc/tlb.c

@@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	/* *I*G - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
 #if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)

board/freescale/p1_twr/tlb.c

@@ -67,7 +67,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #ifdef CONFIG_SYS_RAMBOOT
 	/* *I*G - eSDHC boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 #endif
 

board/freescale/t102xqds/tlb.c

@@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
 	/* entry 14 and 15 has been used hard coded, they will be disabled

board/freescale/t102xrdb/tlb.c

@@ -102,11 +102,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
 	/* entry 14 and 15 has been used hard coded, they will be disabled

board/freescale/t104xrdb/tlb.c

@@ -120,11 +120,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
 };

board/freescale/t208xqds/tlb.c

@@ -145,7 +145,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
 };

board/freescale/t208xrdb/tlb.c

@@ -144,7 +144,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
 

board/freescale/t4qds/tlb.c

@@ -139,7 +139,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif
 };

board/freescale/t4rdb/tlb.c

@@ -116,7 +116,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 18, BOOKE_PAGESZ_2G, 1)
 #endif
 };

board/gdsys/p1022/tlb.c

@@ -65,7 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifdef CONFIG_SYS_RAMBOOT
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 6, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif

board/sbc8548/tlb.c

@@ -66,7 +66,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * 0xf0000000	64M	LBC SDRAM First half
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 3, BOOKE_PAGESZ_64M, 1),
 
 	/*
@@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
 		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 #endif
 

include/configs/T104xRDB.h

@@ -634,6 +634,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
 #endif
 #endif
 

include/configs/p1_p2_rdb_pc.h

@@ -782,6 +782,7 @@
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
 #endif
 #endif