sunxi: Set PLL lock enable bits for R40

According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.

This patch enables it for all the PLLs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

arch/arm/include/asm/arch-sunxi/clock_sun6i.h

@@ -142,6 +142,8 @@ struct sunxi_ccm_reg {
 	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
 	u32 reserved25[5];
 	u32 ccu_sec_switch;	/* 0x2f0 CCU Security Switch, H3 only */
+	u32 reserved26[11];
+	u32 pll_lock_ctrl;	/* 0x320 PLL lock control, R40 only */
 };
 
 /* apb2 bit field */

arch/arm/mach-sunxi/clock_sun6i.c

@@ -35,6 +35,11 @@ void clock_init_safe(void)
 	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
 #endif
 
+#ifdef CONFIG_MACH_SUN8I_R40
+	/* Set PLL lock enable bits and switch to old lock mode */
+	writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
+#endif
+
 	clock_set_pll1(408000000);
 
 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);