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@@ -24,7 +24,7 @@
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#define COMPHY_SEL_ADDR MVEBU_REG(0x0183FC)
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#define rf_compy_select(lane) (0x1 << (((lane) == 1) ? 4 : 0))
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-#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (lane) * 0x28)
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+#define COMPHY_PHY_CFG1_ADDR(lane) MVEBU_REG(0x018300 + (1 - lane) * 0x28)
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#define rb_pin_pu_iveref BIT(1)
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#define rb_pin_reset_core BIT(11)
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#define rb_pin_reset_comphy BIT(12)
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@@ -38,7 +38,7 @@
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#define rf_gen_tx_select (0x0F << rf_gen_tx_sel_shift)
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#define rb_phy_rx_init BIT(30)
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-#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (lane) * 0x28)
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+#define COMPHY_PHY_STAT1_ADDR(lane) MVEBU_REG(0x018318 + (1 - lane) * 0x28)
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#define rb_rx_init_done BIT(0)
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#define rb_pll_ready_rx BIT(2)
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#define rb_pll_ready_tx BIT(3)
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