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@@ -39,6 +39,19 @@ void socfpga_per_reset(u32 reset, int set)
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clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
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}
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+/*
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+ * Assert reset on every peripheral but L4WD0.
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+ * Watchdog must be kept intact to prevent glitches
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+ * and/or hangs.
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+ */
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+void socfpga_per_reset_all(void)
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+{
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+ const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
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+
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+ writel(~l4wd0, &reset_manager_base->per_mod_reset);
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+ writel(0xffffffff, &reset_manager_base->per2_mod_reset);
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+}
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+
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/*
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* Write the reset manager register to cause reset
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*/
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