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@@ -75,6 +75,19 @@ struct lpc32xx_nand_slc_regs {
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#define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
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#define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
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+/* NAND ECC Layout for small page NAND devices
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+ * Note: For large page devices, the default layouts are used. */
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+static struct nand_ecclayout lpc32xx_nand_oob_16 = {
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+ .eccbytes = 6,
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+ .eccpos = {10, 11, 12, 13, 14, 15},
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+ .oobfree = {
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+ {.offset = 0,
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+ . length = 4},
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+ {.offset = 6,
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+ . length = 4}
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+ }
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+};
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+
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#if defined(CONFIG_DMA_LPC32XX)
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#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
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@@ -563,13 +576,16 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
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#endif
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/*
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- * Use default ECC layout, but these values are predefined
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+ * These values are predefined
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* for both small and large page NAND flash devices.
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*/
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lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
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lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
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lpc32xx_chip->ecc.strength = 1;
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+ if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
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+ lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16;
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+
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#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
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lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
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#endif
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