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@@ -1,7 +1,6 @@
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/dts-v1/;
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-#include <dt-bindings/input/input.h>
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-#include "tegra124.dtsi"
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+#include "tegra124-nyan.dtsi"
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/ {
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model = "Acer Chromebook 13 CB5-311";
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@@ -9,6 +8,7 @@
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aliases {
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console = &uarta;
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+ stdout-path = &uarta;
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i2c0 = "/i2c@7000d000";
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i2c1 = "/i2c@7000c000";
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i2c2 = "/i2c@7000c400";
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@@ -23,14 +23,13 @@
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spi1 = "/spi@7000da00";
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usb0 = "/usb@7d000000";
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usb1 = "/usb@7d008000";
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- };
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-
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- memory {
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- reg = <0x80000000 0x80000000>;
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+ usb2 = "/usb@7d004000";
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};
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host1x@50000000 {
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+ u-boot,dm-pre-reloc;
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dc@54200000 {
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+ u-boot,dm-pre-reloc;
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display-timings {
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timing@0 {
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clock-frequency = <69500000>;
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@@ -46,372 +45,1337 @@
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};
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};
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- sor@54540000 {
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- status = "okay";
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-
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- nvidia,dpaux = <&dpaux>;
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- nvidia,panel = <&panel>;
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- };
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-
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- dpaux@545c0000 {
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- status = "okay";
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- };
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- };
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-
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- serial@70006000 {
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- /* Debug connector on the bottom of the board near SD card. */
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- status = "okay";
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- };
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-
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- pwm@7000a000 {
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- status = "okay";
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- };
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-
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- i2c@7000c000 {
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- status = "okay";
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- clock-frequency = <100000>;
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-
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- acodec: audio-codec@10 {
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- compatible = "maxim,max98090";
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- reg = <0x10>;
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- interrupt-parent = <&gpio>;
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- interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
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- };
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-
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- temperature-sensor@4c {
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- compatible = "ti,tmp451";
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- reg = <0x4c>;
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- interrupt-parent = <&gpio>;
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- interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
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-
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- #thermal-sensor-cells = <1>;
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- };
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- };
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-
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- i2c@7000c400 {
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- status = "okay";
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- clock-frequency = <100000>;
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- };
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-
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- i2c@7000c500 {
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- status = "okay";
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- clock-frequency = <400000>;
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-
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- tpm@20 {
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- compatible = "infineon,slb9645tt";
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- reg = <0x20>;
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- };
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- };
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-
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- hdmi_ddc: i2c@7000c700 {
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- status = "okay";
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- clock-frequency = <100000>;
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- };
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-
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- i2c@7000d000 {
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- status = "okay";
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- clock-frequency = <400000>;
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-
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- pmic: pmic@40 {
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- compatible = "ams,as3722";
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- reg = <0x40>;
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- interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
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-
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- ams,system-power-controller;
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-
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- #interrupt-cells = <2>;
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- interrupt-controller;
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-
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- gpio-controller;
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- #gpio-cells = <2>;
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-
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- pinctrl-names = "default";
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- pinctrl-0 = <&as3722_default>;
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-
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- as3722_default: pinmux {
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- gpio0 {
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- pins = "gpio0";
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- function = "gpio";
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- bias-pull-down;
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- };
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-
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- gpio1 {
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- pins = "gpio1";
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- function = "gpio";
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- bias-pull-up;
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- };
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-
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- gpio2_4_7 {
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- pins = "gpio2", "gpio4", "gpio7";
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- function = "gpio";
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- bias-pull-up;
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- };
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-
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- gpio3_6 {
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- pins = "gpio3", "gpio6";
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- bias-high-impedance;
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- };
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-
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- gpio5 {
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- pins = "gpio5";
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- function = "clk32k-out";
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- bias-pull-down;
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- };
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- };
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- };
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- };
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-
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- spi@7000d400 {
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- status = "okay";
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- spi-deactivate-delay = <200>;
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- spi-max-frequency = <3000000>;
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-
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- cros_ec: cros-ec@0 {
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- compatible = "google,cros-ec-spi";
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- spi-max-frequency = <3000000>;
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- interrupt-parent = <&gpio>;
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- interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
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- ec-interrupt = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
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- reg = <0>;
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-
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- google,cros-ec-spi-msg-delay = <2000>;
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-
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- i2c-tunnel {
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- compatible = "google,cros-ec-i2c-tunnel";
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- google,remote-bus = <0>;
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-
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- charger: bq24735@9 {
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- compatible = "ti,bq24735";
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- reg = <0x9>;
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- interrupt-parent = <&gpio>;
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- interrupts = <TEGRA_GPIO(J, 0)
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- GPIO_ACTIVE_HIGH>;
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- ti,ac-detect-gpios = <&gpio
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- TEGRA_GPIO(J, 0)
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- GPIO_ACTIVE_HIGH>;
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- };
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-
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- battery: sbs-battery@b {
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- compatible = "sbs,sbs-battery";
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- reg = <0xb>;
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- sbs,i2c-retry-count = <2>;
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- sbs,poll-retry-count = <10>;
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- power-supplies = <&charger>;
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- };
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- };
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- };
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- };
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-
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- spi@7000da00 {
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- status = "okay";
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- spi-max-frequency = <25000000>;
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-
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- flash@0 {
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- compatible = "winbond,w25q32dw";
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- reg = <0>;
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- };
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- };
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-
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- pmc@7000e400 {
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- nvidia,invert-interrupt;
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- nvidia,suspend-mode = <0>;
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- nvidia,cpu-pwr-good-time = <500>;
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- nvidia,cpu-pwr-off-time = <300>;
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- nvidia,core-pwr-good-time = <641 3845>;
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- nvidia,core-pwr-off-time = <61036>;
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- nvidia,core-power-req-active-high;
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- nvidia,sys-clock-req-active-high;
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- };
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-
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- hda@70030000 {
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- status = "okay";
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- };
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-
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- sdhci@700b0000 { /* WiFi/BT on this bus */
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- status = "okay";
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- power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
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- bus-width = <4>;
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- no-1-8-v;
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- non-removable;
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- };
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-
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- sdhci@700b0400 { /* SD Card on this bus */
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- status = "okay";
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- cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
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- power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
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- wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
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- bus-width = <4>;
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- no-1-8-v;
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- };
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-
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- sdhci@700b0600 { /* eMMC on this bus */
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- status = "okay";
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- bus-width = <8>;
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- no-1-8-v;
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- non-removable;
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- };
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-
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- ahub@70300000 {
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- i2s@70301100 {
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- status = "okay";
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- };
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- };
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-
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- usb@7d000000 { /* Rear external USB port. */
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- status = "okay";
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- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
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- };
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-
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- usb-phy@7d000000 {
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- status = "okay";
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- };
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-
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- usb@7d004000 { /* Internal webcam. */
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- status = "okay";
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- };
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-
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- usb-phy@7d004000 {
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- status = "okay";
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- };
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-
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- usb@7d008000 { /* Left external USB port. */
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- status = "okay";
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- nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
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- };
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-
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- usb-phy@7d008000 {
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- status = "okay";
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- };
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-
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- backlight: backlight {
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- compatible = "pwm-backlight";
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-
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- enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
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- power-supply = <&vdd_led>;
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- pwms = <&pwm 1 1000000>;
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-
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- default-brightness-level = <224>;
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- brightness-levels =
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- < 0 1 2 3 4 5 6 7
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- 8 9 10 11 12 13 14 15
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- 16 17 18 19 20 21 22 23
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- 24 25 26 27 28 29 30 31
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- 32 33 34 35 36 37 38 39
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- 40 41 42 43 44 45 46 47
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- 48 49 50 51 52 53 54 55
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- 56 57 58 59 60 61 62 63
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- 64 65 66 67 68 69 70 71
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- 72 73 74 75 76 77 78 79
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- 80 81 82 83 84 85 86 87
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- 88 89 90 91 92 93 94 95
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- 96 97 98 99 100 101 102 103
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- 104 105 106 107 108 109 110 111
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- 112 113 114 115 116 117 118 119
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- 120 121 122 123 124 125 126 127
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- 128 129 130 131 132 133 134 135
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- 136 137 138 139 140 141 142 143
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- 144 145 146 147 148 149 150 151
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- 152 153 154 155 156 157 158 159
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- 160 161 162 163 164 165 166 167
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- 168 169 170 171 172 173 174 175
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- 176 177 178 179 180 181 182 183
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- 184 185 186 187 188 189 190 191
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- 192 193 194 195 196 197 198 199
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- 200 201 202 203 204 205 206 207
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- 208 209 210 211 212 213 214 215
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- 216 217 218 219 220 221 222 223
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- 224 225 226 227 228 229 230 231
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- 232 233 234 235 236 237 238 239
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- 240 241 242 243 244 245 246 247
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- 248 249 250 251 252 253 254 255
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- 256>;
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- };
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-
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- clocks {
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- compatible = "simple-bus";
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- clk32k_in: clock@0 {
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- compatible = "fixed-clock";
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- reg = <0>;
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- #clock-cells = <0>;
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- clock-frequency = <32768>;
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- };
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- };
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-
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- gpio@6000d000 {
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- u-boot,dm-pre-reloc;
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- };
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-
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- gpio-keys {
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- compatible = "gpio-keys";
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-
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- lid {
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- label = "Lid";
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- gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
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- linux,input-type = <5>;
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- linux,code = <KEY_RESERVED>;
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- debounce-interval = <1>;
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- gpio-key,wakeup;
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+ dc@54240000 {
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+ status = "disabled";
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};
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- power {
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- label = "Power";
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- gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
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- linux,code = <KEY_POWER>;
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- debounce-interval = <30>;
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- gpio-key,wakeup;
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- };
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};
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panel: panel {
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compatible = "auo,b133xtn01";
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backlight = <&backlight>;
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+ ddc-i2c-bus = <&dpaux>;
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};
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- regulators {
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- compatible = "simple-bus";
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- #address-cells = <1>;
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- #size-cells = <0>;
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- vdd_led: regulator@5 {
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- compatible = "regulator-fixed";
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- reg = <5>;
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- regulator-name = "+VDD_LED";
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- gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
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- enable-active-high;
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- };
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+ sdhci@0,700b0400 { /* SD Card on this bus */
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+ wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
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};
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sound {
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compatible = "nvidia,tegra-audio-max98090-nyan-big",
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+ "nvidia,tegra-audio-max98090-nyan",
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"nvidia,tegra-audio-max98090";
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- nvidia,model = "Acer Chromebook 13";
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-
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- nvidia,audio-routing =
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- "Headphones", "HPR",
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- "Headphones", "HPL",
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- "Speakers", "SPKR",
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- "Speakers", "SPKL",
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- "Mic Jack", "MICBIAS",
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- "DMICL", "Int Mic",
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- "DMICR", "Int Mic",
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- "IN34", "Mic Jack";
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-
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- nvidia,i2s-controller = <&tegra_i2s1>;
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- nvidia,audio-codec = <&acodec>;
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+ nvidia,model = "GoogleNyanBig";
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+ };
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- clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
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- <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
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- <&tegra_car TEGRA124_CLK_EXTERN1>;
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- clock-names = "pll_a", "pll_a_out0", "mclk";
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+ pinmux@0,70000868 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinmux_default>;
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- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
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+ pinmux_default: common {
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+ clk_32k_out_pa0 {
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+ nvidia,pins = "clk_32k_out_pa0";
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+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
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+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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+ };
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+ uart3_cts_n_pa1 {
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+ nvidia,pins = "uart3_cts_n_pa1";
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+ nvidia,function = "gmi";
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+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
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+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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+ };
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+ dap2_fs_pa2 {
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+ nvidia,pins = "dap2_fs_pa2";
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+ nvidia,function = "i2s1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ dap2_sclk_pa3 {
|
|
|
+ nvidia,pins = "dap2_sclk_pa3";
|
|
|
+ nvidia,function = "i2s1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ dap2_din_pa4 {
|
|
|
+ nvidia,pins = "dap2_din_pa4";
|
|
|
+ nvidia,function = "i2s1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ dap2_dout_pa5 {
|
|
|
+ nvidia,pins = "dap2_dout_pa5";
|
|
|
+ nvidia,function = "i2s1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_clk_pa6 {
|
|
|
+ nvidia,pins = "sdmmc3_clk_pa6";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_cmd_pa7 {
|
|
|
+ nvidia,pins = "sdmmc3_cmd_pa7";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pb0 {
|
|
|
+ nvidia,pins = "pb0";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pb1 {
|
|
|
+ nvidia,pins = "pb1";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_dat3_pb4 {
|
|
|
+ nvidia,pins = "sdmmc3_dat3_pb4";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_dat2_pb5 {
|
|
|
+ nvidia,pins = "sdmmc3_dat2_pb5";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_dat1_pb6 {
|
|
|
+ nvidia,pins = "sdmmc3_dat1_pb6";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_dat0_pb7 {
|
|
|
+ nvidia,pins = "sdmmc3_dat0_pb7";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ uart3_rts_n_pc0 {
|
|
|
+ nvidia,pins = "uart3_rts_n_pc0";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ uart2_txd_pc2 {
|
|
|
+ nvidia,pins = "uart2_txd_pc2";
|
|
|
+ nvidia,function = "irda";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ uart2_rxd_pc3 {
|
|
|
+ nvidia,pins = "uart2_rxd_pc3";
|
|
|
+ nvidia,function = "irda";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gen1_i2c_scl_pc4 {
|
|
|
+ nvidia,pins = "gen1_i2c_scl_pc4";
|
|
|
+ nvidia,function = "i2c1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ gen1_i2c_sda_pc5 {
|
|
|
+ nvidia,pins = "gen1_i2c_sda_pc5";
|
|
|
+ nvidia,function = "i2c1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pc7 {
|
|
|
+ nvidia,pins = "pc7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pg0 {
|
|
|
+ nvidia,pins = "pg0";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pg1 {
|
|
|
+ nvidia,pins = "pg1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pg2 {
|
|
|
+ nvidia,pins = "pg2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pg3 {
|
|
|
+ nvidia,pins = "pg3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pg4 {
|
|
|
+ nvidia,pins = "pg4";
|
|
|
+ nvidia,function = "spi4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pg5 {
|
|
|
+ nvidia,pins = "pg5";
|
|
|
+ nvidia,function = "spi4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pg6 {
|
|
|
+ nvidia,pins = "pg6";
|
|
|
+ nvidia,function = "spi4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pg7 {
|
|
|
+ nvidia,pins = "pg7";
|
|
|
+ nvidia,function = "spi4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ ph0 {
|
|
|
+ nvidia,pins = "ph0";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ph1 {
|
|
|
+ nvidia,pins = "ph1";
|
|
|
+ nvidia,function = "pwm1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ph2 {
|
|
|
+ nvidia,pins = "ph2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ ph3 {
|
|
|
+ nvidia,pins = "ph3";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ph4 {
|
|
|
+ nvidia,pins = "ph4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ ph5 {
|
|
|
+ nvidia,pins = "ph5";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ph6 {
|
|
|
+ nvidia,pins = "ph6";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ ph7 {
|
|
|
+ nvidia,pins = "ph7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pi0 {
|
|
|
+ nvidia,pins = "pi0";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pi1 {
|
|
|
+ nvidia,pins = "pi1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pi2 {
|
|
|
+ nvidia,pins = "pi2";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pi3 {
|
|
|
+ nvidia,pins = "pi3";
|
|
|
+ nvidia,function = "spi4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pi4 {
|
|
|
+ nvidia,pins = "pi4";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pi5 {
|
|
|
+ nvidia,pins = "pi5";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pi6 {
|
|
|
+ nvidia,pins = "pi6";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pi7 {
|
|
|
+ nvidia,pins = "pi7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pj0 {
|
|
|
+ nvidia,pins = "pj0";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pj2 {
|
|
|
+ nvidia,pins = "pj2";
|
|
|
+ nvidia,function = "rsvd1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ uart2_cts_n_pj5 {
|
|
|
+ nvidia,pins = "uart2_cts_n_pj5";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ uart2_rts_n_pj6 {
|
|
|
+ nvidia,pins = "uart2_rts_n_pj6";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pj7 {
|
|
|
+ nvidia,pins = "pj7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pk0 {
|
|
|
+ nvidia,pins = "pk0";
|
|
|
+ nvidia,function = "rsvd1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pk1 {
|
|
|
+ nvidia,pins = "pk1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pk2 {
|
|
|
+ nvidia,pins = "pk2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pk3 {
|
|
|
+ nvidia,pins = "pk3";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pk4 {
|
|
|
+ nvidia,pins = "pk4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ spdif_out_pk5 {
|
|
|
+ nvidia,pins = "spdif_out_pk5";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ spdif_in_pk6 {
|
|
|
+ nvidia,pins = "spdif_in_pk6";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pk7 {
|
|
|
+ nvidia,pins = "pk7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ dap1_fs_pn0 {
|
|
|
+ nvidia,pins = "dap1_fs_pn0";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap1_din_pn1 {
|
|
|
+ nvidia,pins = "dap1_din_pn1";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap1_dout_pn2 {
|
|
|
+ nvidia,pins = "dap1_dout_pn2";
|
|
|
+ nvidia,function = "i2s0";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap1_sclk_pn3 {
|
|
|
+ nvidia,pins = "dap1_sclk_pn3";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ usb_vbus_en0_pn4 {
|
|
|
+ nvidia,pins = "usb_vbus_en0_pn4";
|
|
|
+ nvidia,function = "usb";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ usb_vbus_en1_pn5 {
|
|
|
+ nvidia,pins = "usb_vbus_en1_pn5";
|
|
|
+ nvidia,function = "usb";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ hdmi_int_pn7 {
|
|
|
+ nvidia,pins = "hdmi_int_pn7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data7_po0 {
|
|
|
+ nvidia,pins = "ulpi_data7_po0";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data0_po1 {
|
|
|
+ nvidia,pins = "ulpi_data0_po1";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data1_po2 {
|
|
|
+ nvidia,pins = "ulpi_data1_po2";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data2_po3 {
|
|
|
+ nvidia,pins = "ulpi_data2_po3";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data3_po4 {
|
|
|
+ nvidia,pins = "ulpi_data3_po4";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data4_po5 {
|
|
|
+ nvidia,pins = "ulpi_data4_po5";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data5_po6 {
|
|
|
+ nvidia,pins = "ulpi_data5_po6";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_data6_po7 {
|
|
|
+ nvidia,pins = "ulpi_data6_po7";
|
|
|
+ nvidia,function = "ulpi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap3_fs_pp0 {
|
|
|
+ nvidia,pins = "dap3_fs_pp0";
|
|
|
+ nvidia,function = "i2s2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap3_din_pp1 {
|
|
|
+ nvidia,pins = "dap3_din_pp1";
|
|
|
+ nvidia,function = "i2s2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap3_dout_pp2 {
|
|
|
+ nvidia,pins = "dap3_dout_pp2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap3_sclk_pp3 {
|
|
|
+ nvidia,pins = "dap3_sclk_pp3";
|
|
|
+ nvidia,function = "rsvd3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap4_fs_pp4 {
|
|
|
+ nvidia,pins = "dap4_fs_pp4";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap4_din_pp5 {
|
|
|
+ nvidia,pins = "dap4_din_pp5";
|
|
|
+ nvidia,function = "rsvd3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap4_dout_pp6 {
|
|
|
+ nvidia,pins = "dap4_dout_pp6";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap4_sclk_pp7 {
|
|
|
+ nvidia,pins = "dap4_sclk_pp7";
|
|
|
+ nvidia,function = "rsvd3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_col0_pq0 {
|
|
|
+ nvidia,pins = "kb_col0_pq0";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_col1_pq1 {
|
|
|
+ nvidia,pins = "kb_col1_pq1";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_col2_pq2 {
|
|
|
+ nvidia,pins = "kb_col2_pq2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_col3_pq3 {
|
|
|
+ nvidia,pins = "kb_col3_pq3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_col4_pq4 {
|
|
|
+ nvidia,pins = "kb_col4_pq4";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_col5_pq5 {
|
|
|
+ nvidia,pins = "kb_col5_pq5";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_col6_pq6 {
|
|
|
+ nvidia,pins = "kb_col6_pq6";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_col7_pq7 {
|
|
|
+ nvidia,pins = "kb_col7_pq7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_row0_pr0 {
|
|
|
+ nvidia,pins = "kb_row0_pr0";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row1_pr1 {
|
|
|
+ nvidia,pins = "kb_row1_pr1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_row2_pr2 {
|
|
|
+ nvidia,pins = "kb_row2_pr2";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row3_pr3 {
|
|
|
+ nvidia,pins = "kb_row3_pr3";
|
|
|
+ nvidia,function = "kbc";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row4_pr4 {
|
|
|
+ nvidia,pins = "kb_row4_pr4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_row5_pr5 {
|
|
|
+ nvidia,pins = "kb_row5_pr5";
|
|
|
+ nvidia,function = "rsvd3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row6_pr6 {
|
|
|
+ nvidia,pins = "kb_row6_pr6";
|
|
|
+ nvidia,function = "kbc";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row7_pr7 {
|
|
|
+ nvidia,pins = "kb_row7_pr7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_row8_ps0 {
|
|
|
+ nvidia,pins = "kb_row8_ps0";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row9_ps1 {
|
|
|
+ nvidia,pins = "kb_row9_ps1";
|
|
|
+ nvidia,function = "uarta";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row10_ps2 {
|
|
|
+ nvidia,pins = "kb_row10_ps2";
|
|
|
+ nvidia,function = "uarta";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_row11_ps3 {
|
|
|
+ nvidia,pins = "kb_row11_ps3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row12_ps4 {
|
|
|
+ nvidia,pins = "kb_row12_ps4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row13_ps5 {
|
|
|
+ nvidia,pins = "kb_row13_ps5";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row14_ps6 {
|
|
|
+ nvidia,pins = "kb_row14_ps6";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row15_ps7 {
|
|
|
+ nvidia,pins = "kb_row15_ps7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ kb_row16_pt0 {
|
|
|
+ nvidia,pins = "kb_row16_pt0";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ kb_row17_pt1 {
|
|
|
+ nvidia,pins = "kb_row17_pt1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ gen2_i2c_scl_pt5 {
|
|
|
+ nvidia,pins = "gen2_i2c_scl_pt5";
|
|
|
+ nvidia,function = "i2c2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ gen2_i2c_sda_pt6 {
|
|
|
+ nvidia,pins = "gen2_i2c_sda_pt6";
|
|
|
+ nvidia,function = "i2c2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_cmd_pt7 {
|
|
|
+ nvidia,pins = "sdmmc4_cmd_pt7";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pu0 {
|
|
|
+ nvidia,pins = "pu0";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pu1 {
|
|
|
+ nvidia,pins = "pu1";
|
|
|
+ nvidia,function = "rsvd1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pu2 {
|
|
|
+ nvidia,pins = "pu2";
|
|
|
+ nvidia,function = "rsvd1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pu3 {
|
|
|
+ nvidia,pins = "pu3";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pu4 {
|
|
|
+ nvidia,pins = "pu4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pu5 {
|
|
|
+ nvidia,pins = "pu5";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pu6 {
|
|
|
+ nvidia,pins = "pu6";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pv0 {
|
|
|
+ nvidia,pins = "pv0";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pv1 {
|
|
|
+ nvidia,pins = "pv1";
|
|
|
+ nvidia,function = "rsvd1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_cd_n_pv2 {
|
|
|
+ nvidia,pins = "sdmmc3_cd_n_pv2";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc1_wp_n_pv3 {
|
|
|
+ nvidia,pins = "sdmmc1_wp_n_pv3";
|
|
|
+ nvidia,function = "sdmmc1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ddc_scl_pv4 {
|
|
|
+ nvidia,pins = "ddc_scl_pv4";
|
|
|
+ nvidia,function = "i2c4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ddc_sda_pv5 {
|
|
|
+ nvidia,pins = "ddc_sda_pv5";
|
|
|
+ nvidia,function = "i2c4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gpio_w2_aud_pw2 {
|
|
|
+ nvidia,pins = "gpio_w2_aud_pw2";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gpio_w3_aud_pw3 {
|
|
|
+ nvidia,pins = "gpio_w3_aud_pw3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ dap_mclk1_pw4 {
|
|
|
+ nvidia,pins = "dap_mclk1_pw4";
|
|
|
+ nvidia,function = "extperiph1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ clk2_out_pw5 {
|
|
|
+ nvidia,pins = "clk2_out_pw5";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ uart3_txd_pw6 {
|
|
|
+ nvidia,pins = "uart3_txd_pw6";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ uart3_rxd_pw7 {
|
|
|
+ nvidia,pins = "uart3_rxd_pw7";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dvfs_pwm_px0 {
|
|
|
+ nvidia,pins = "dvfs_pwm_px0";
|
|
|
+ nvidia,function = "cldvfs";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gpio_x1_aud_px1 {
|
|
|
+ nvidia,pins = "gpio_x1_aud_px1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ dvfs_clk_px2 {
|
|
|
+ nvidia,pins = "dvfs_clk_px2";
|
|
|
+ nvidia,function = "cldvfs";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gpio_x3_aud_px3 {
|
|
|
+ nvidia,pins = "gpio_x3_aud_px3";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gpio_x4_aud_px4 {
|
|
|
+ nvidia,pins = "gpio_x4_aud_px4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ gpio_x5_aud_px5 {
|
|
|
+ nvidia,pins = "gpio_x5_aud_px5";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gpio_x6_aud_px6 {
|
|
|
+ nvidia,pins = "gpio_x6_aud_px6";
|
|
|
+ nvidia,function = "gmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ gpio_x7_aud_px7 {
|
|
|
+ nvidia,pins = "gpio_x7_aud_px7";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_clk_py0 {
|
|
|
+ nvidia,pins = "ulpi_clk_py0";
|
|
|
+ nvidia,function = "spi1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_dir_py1 {
|
|
|
+ nvidia,pins = "ulpi_dir_py1";
|
|
|
+ nvidia,function = "spi1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ ulpi_nxt_py2 {
|
|
|
+ nvidia,pins = "ulpi_nxt_py2";
|
|
|
+ nvidia,function = "spi1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ ulpi_stp_py3 {
|
|
|
+ nvidia,pins = "ulpi_stp_py3";
|
|
|
+ nvidia,function = "spi1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ sdmmc1_dat3_py4 {
|
|
|
+ nvidia,pins = "sdmmc1_dat3_py4";
|
|
|
+ nvidia,function = "sdmmc1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc1_dat2_py5 {
|
|
|
+ nvidia,pins = "sdmmc1_dat2_py5";
|
|
|
+ nvidia,function = "sdmmc1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc1_dat1_py6 {
|
|
|
+ nvidia,pins = "sdmmc1_dat1_py6";
|
|
|
+ nvidia,function = "sdmmc1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc1_dat0_py7 {
|
|
|
+ nvidia,pins = "sdmmc1_dat0_py7";
|
|
|
+ nvidia,function = "sdmmc1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc1_clk_pz0 {
|
|
|
+ nvidia,pins = "sdmmc1_clk_pz0";
|
|
|
+ nvidia,function = "sdmmc1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc1_cmd_pz1 {
|
|
|
+ nvidia,pins = "sdmmc1_cmd_pz1";
|
|
|
+ nvidia,function = "sdmmc1";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pwr_i2c_scl_pz6 {
|
|
|
+ nvidia,pins = "pwr_i2c_scl_pz6";
|
|
|
+ nvidia,function = "i2cpwr";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pwr_i2c_sda_pz7 {
|
|
|
+ nvidia,pins = "pwr_i2c_sda_pz7";
|
|
|
+ nvidia,function = "i2cpwr";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat0_paa0 {
|
|
|
+ nvidia,pins = "sdmmc4_dat0_paa0";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat1_paa1 {
|
|
|
+ nvidia,pins = "sdmmc4_dat1_paa1";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat2_paa2 {
|
|
|
+ nvidia,pins = "sdmmc4_dat2_paa2";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat3_paa3 {
|
|
|
+ nvidia,pins = "sdmmc4_dat3_paa3";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat4_paa4 {
|
|
|
+ nvidia,pins = "sdmmc4_dat4_paa4";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat5_paa5 {
|
|
|
+ nvidia,pins = "sdmmc4_dat5_paa5";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat6_paa6 {
|
|
|
+ nvidia,pins = "sdmmc4_dat6_paa6";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_dat7_paa7 {
|
|
|
+ nvidia,pins = "sdmmc4_dat7_paa7";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ pbb0 {
|
|
|
+ nvidia,pins = "pbb0";
|
|
|
+ nvidia,function = "vgp6";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ cam_i2c_scl_pbb1 {
|
|
|
+ nvidia,pins = "cam_i2c_scl_pbb1";
|
|
|
+ nvidia,function = "rsvd3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ cam_i2c_sda_pbb2 {
|
|
|
+ nvidia,pins = "cam_i2c_sda_pbb2";
|
|
|
+ nvidia,function = "rsvd3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pbb3 {
|
|
|
+ nvidia,pins = "pbb3";
|
|
|
+ nvidia,function = "vgp3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pbb4 {
|
|
|
+ nvidia,pins = "pbb4";
|
|
|
+ nvidia,function = "vgp4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pbb5 {
|
|
|
+ nvidia,pins = "pbb5";
|
|
|
+ nvidia,function = "rsvd3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pbb6 {
|
|
|
+ nvidia,pins = "pbb6";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pbb7 {
|
|
|
+ nvidia,pins = "pbb7";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ cam_mclk_pcc0 {
|
|
|
+ nvidia,pins = "cam_mclk_pcc0";
|
|
|
+ nvidia,function = "vi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pcc1 {
|
|
|
+ nvidia,pins = "pcc1";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pcc2 {
|
|
|
+ nvidia,pins = "pcc2";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ sdmmc4_clk_pcc4 {
|
|
|
+ nvidia,pins = "sdmmc4_clk_pcc4";
|
|
|
+ nvidia,function = "sdmmc4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ clk2_req_pcc5 {
|
|
|
+ nvidia,pins = "clk2_req_pcc5";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pex_l0_rst_n_pdd1 {
|
|
|
+ nvidia,pins = "pex_l0_rst_n_pdd1";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pex_l0_clkreq_n_pdd2 {
|
|
|
+ nvidia,pins = "pex_l0_clkreq_n_pdd2";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pex_wake_n_pdd3 {
|
|
|
+ nvidia,pins = "pex_wake_n_pdd3";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pex_l1_rst_n_pdd5 {
|
|
|
+ nvidia,pins = "pex_l1_rst_n_pdd5";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pex_l1_clkreq_n_pdd6 {
|
|
|
+ nvidia,pins = "pex_l1_clkreq_n_pdd6";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ clk3_out_pee0 {
|
|
|
+ nvidia,pins = "clk3_out_pee0";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ clk3_req_pee1 {
|
|
|
+ nvidia,pins = "clk3_req_pee1";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ dap_mclk1_req_pee2 {
|
|
|
+ nvidia,pins = "dap_mclk1_req_pee2";
|
|
|
+ nvidia,function = "rsvd4";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ hdmi_cec_pee3 {
|
|
|
+ nvidia,pins = "hdmi_cec_pee3";
|
|
|
+ nvidia,function = "cec";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_clk_lb_out_pee4 {
|
|
|
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ sdmmc3_clk_lb_in_pee5 {
|
|
|
+ nvidia,pins = "sdmmc3_clk_lb_in_pee5";
|
|
|
+ nvidia,function = "sdmmc3";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ dp_hpd_pff0 {
|
|
|
+ nvidia,pins = "dp_hpd_pff0";
|
|
|
+ nvidia,function = "dp";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ usb_vbus_en2_pff1 {
|
|
|
+ nvidia,pins = "usb_vbus_en2_pff1";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pff2 {
|
|
|
+ nvidia,pins = "pff2";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ core_pwr_req {
|
|
|
+ nvidia,pins = "core_pwr_req";
|
|
|
+ nvidia,function = "pwron";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ cpu_pwr_req {
|
|
|
+ nvidia,pins = "cpu_pwr_req";
|
|
|
+ nvidia,function = "cpu";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ pwr_int_n {
|
|
|
+ nvidia,pins = "pwr_int_n";
|
|
|
+ nvidia,function = "pmi";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ reset_out_n {
|
|
|
+ nvidia,pins = "reset_out_n";
|
|
|
+ nvidia,function = "reset_out_n";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ owr {
|
|
|
+ nvidia,pins = "owr";
|
|
|
+ nvidia,function = "rsvd2";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ clk_32k_in {
|
|
|
+ nvidia,pins = "clk_32k_in";
|
|
|
+ nvidia,function = "clk";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
+ };
|
|
|
+ jtag_rtck {
|
|
|
+ nvidia,pins = "jtag_rtck";
|
|
|
+ nvidia,function = "rtck";
|
|
|
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
+ };
|
|
|
+ };
|
|
|
};
|
|
|
};
|
|
|
-
|
|
|
-#include "cros-ec-keyboard.dtsi"
|