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@@ -285,18 +285,33 @@ static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
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return 0;
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}
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-static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
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+static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
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{
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u32 data;
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+ unsigned long start;
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+ int ret;
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+ /* No idea if this is long enough or too long */
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+ int timeout_ms = 1000;
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/* Dummy read followed by PHY read/write command. */
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- ag7xxx_switch_reg_read(bus, 0x98, &data);
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+ ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
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+ if (ret < 0)
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+ return ret;
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data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
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- ag7xxx_switch_reg_write(bus, 0x98, data);
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+ ret = ag7xxx_switch_reg_write(bus, 0x98, data);
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+ if (ret < 0)
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+ return ret;
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+
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+ start = get_timer(0);
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/* Wait for operation to finish */
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do {
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- ag7xxx_switch_reg_read(bus, 0x98, &data);
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+ ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
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+ if (ret < 0)
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+ return ret;
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+
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+ if (get_timer(start) > timeout_ms)
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+ return -ETIMEDOUT;
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} while (data & BIT(31));
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return data & 0xffff;
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@@ -310,7 +325,11 @@ static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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- ag7xxx_mdio_rw(bus, addr, reg, val);
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+ int ret;
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+
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+ ret = ag7xxx_mdio_rw(bus, addr, reg, val);
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+ if (ret < 0)
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+ return ret;
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return 0;
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}
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