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@@ -64,14 +64,18 @@ static int nand_command(int block, int page, uint32_t offs,
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NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
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NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
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hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
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hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
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/* Row address */
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/* Row address */
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- hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
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- hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
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+ if (cmd != NAND_CMD_RNDOUT) {
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+ hwctrl(&nand_info[0], (page_addr & 0xff),
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+ NAND_CTRL_ALE); /* A[19:12] */
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+ hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
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NAND_CTRL_ALE); /* A[27:20] */
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NAND_CTRL_ALE); /* A[27:20] */
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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- /* One more address cycle for devices > 128MiB */
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- hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
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+ /* One more address cycle for devices > 128MiB */
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+ hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
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NAND_CTRL_ALE); /* A[31:28] */
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NAND_CTRL_ALE); /* A[31:28] */
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#endif
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#endif
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+ }
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+
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hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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if (cmd == NAND_CMD_READ0) {
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if (cmd == NAND_CMD_READ0) {
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