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@@ -14,6 +14,7 @@
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static bool fwcfg_present;
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static bool fwcfg_dma_present;
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+static struct fw_cfg_arch_ops *fwcfg_arch_ops;
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static LIST_HEAD(fw_list);
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@@ -21,17 +22,10 @@ static LIST_HEAD(fw_list);
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static void qemu_fwcfg_read_entry_pio(uint16_t entry,
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uint32_t size, void *address)
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{
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- uint32_t i = 0;
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- uint8_t *data = address;
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+ debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
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+ entry, size, address);
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- /*
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- * writting FW_CFG_INVALID will cause read operation to resume at
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- * last offset, otherwise read will start at offset 0
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- */
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- if (entry != FW_CFG_INVALID)
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- outw(entry, FW_CONTROL_PORT);
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- while (size--)
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- data[i++] = inb(FW_DATA_PORT);
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+ return fwcfg_arch_ops->arch_read_pio(entry, size, address);
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}
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/* Read configuration item using fw_cfg DMA interface */
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@@ -53,13 +47,10 @@ static void qemu_fwcfg_read_entry_dma(uint16_t entry,
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barrier();
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- debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
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- address, size, be32_to_cpu(dma.control));
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-
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- outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
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+ debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
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+ entry, size, address, be32_to_cpu(dma.control));
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- while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
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- __asm__ __volatile__ ("pause");
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+ fwcfg_arch_ops->arch_read_dma(&dma);
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}
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bool qemu_fwcfg_present(void)
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@@ -164,13 +155,18 @@ bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
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return iter->entry == &fw_list;
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}
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-void qemu_fwcfg_init(void)
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+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
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{
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uint32_t qemu;
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uint32_t dma_enabled;
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fwcfg_present = false;
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fwcfg_dma_present = false;
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+ fwcfg_arch_ops = NULL;
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+
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+ if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
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+ return;
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+ fwcfg_arch_ops = ops;
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qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
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if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
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