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crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig

Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.

Signed-off-by: York Sun <york.sun@nxp.com>
York Sun 8 سال پیش
والد
53c953841b
کامیت
2c2e2c9e14
13فایلهای تغییر یافته به همراه115 افزوده شده و 37 حذف شده
مشاهده تقسیم شده نمایش آمار تفاوت ها
  1. 4 0
      arch/arm/Kconfig
  2. 2 0
      arch/arm/cpu/armv7/ls102xa/Kconfig
  3. 4 0
      arch/arm/cpu/armv8/fsl-layerscape/Kconfig
  4. 0 2
      arch/arm/include/asm/arch-fsl-layerscape/config.h
  5. 0 1
      arch/arm/include/asm/arch-ls102xa/config.h
  6. 2 0
      arch/powerpc/Kconfig
  7. 70 0
      arch/powerpc/cpu/mpc85xx/Kconfig
  8. 0 1
      arch/powerpc/include/asm/config.h
  9. 0 30
      arch/powerpc/include/asm/config_mpc85xx.h
  10. 33 0
      drivers/crypto/fsl/Kconfig
  11. 0 1
      include/configs/mx6_common.h
  12. 0 1
      include/configs/mx7_common.h
  13. 0 1
      scripts/config_whitelist.txt

+ 4 - 0
arch/arm/Kconfig
مشاهده فایل 

@@ -464,10 +464,14 @@ config ARCH_MESON
 
 config ARCH_MX7
 
 	bool "Freescale MX7"
 
 	select CPU_V7
 
+	select SYS_FSL_HAS_SEC if SECURE_BOOT
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_MX6
 
 	bool "Freescale MX6"
 
 	select CPU_V7
 
+	select SYS_FSL_HAS_SEC if SECURE_BOOT
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_MX5
 
 	bool "Freescale MX5"

+ 2 - 0
arch/arm/cpu/armv7/ls102xa/Kconfig
مشاهده فایل 

@@ -5,6 +5,8 @@ config ARCH_LS1021A
 
 	select SYS_HAS_SERDES
 
 	select SYS_FSL_DDR_BE
 
 	select SYS_FSL_DDR_VER_50
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_5
 
 
 menu "LS102xA architecture"
 
 	depends on ARCH_LS1021A

+ 4 - 0
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
مشاهده فایل 

@@ -29,10 +29,14 @@ config ARCH_LS2080A
 
 	select SYS_FSL_DDR_LE
 
 	select SYS_FSL_DDR_VER_50
 
 	select SYS_FSL_HAS_DP_DDR
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_5
 
 	select SYS_FSL_SRDS_2
 
 
 config FSL_LSCH2
 
 	bool
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_5
 
 	select SYS_FSL_SRDS_1
 
 	select SYS_HAS_SERDES

+ 0 - 2
arch/arm/include/asm/arch-fsl-layerscape/config.h
مشاهده فایل 

@@ -57,7 +57,6 @@
 
 
 /* SEC */
 
 #define CONFIG_SYS_FSL_SEC_LE
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	5
 
 
 /* Security Monitor */
 
 #define CONFIG_SYS_FSL_SEC_MON_LE
 
@@ -135,7 +134,6 @@
 
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 
 #elif defined(CONFIG_FSL_LSCH2)
 
-#define CONFIG_SYS_FSL_SEC_COMPAT		5
 
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 
 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */

+ 0 - 1
arch/arm/include/asm/arch-ls102xa/config.h
مشاهده فایل 

@@ -114,7 +114,6 @@
 
 #define DCU_LAYER_MAX_NUM			16
 
 
 #ifdef CONFIG_LS102XA
 
-#define CONFIG_SYS_FSL_SEC_COMPAT		5
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 
 #define CONFIG_SYS_FSL_ERRATUM_A009663

+ 2 - 0
arch/powerpc/Kconfig
مشاهده فایل 

@@ -23,6 +23,8 @@ config MPC8260
 
 config MPC83xx
 
 	bool "MPC83xx"
 
 	select CREATE_ARCH_SYMLINK
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 
 config MPC85xx
 
 	bool "MPC85xx"

+ 70 - 0
arch/powerpc/cpu/mpc85xx/Kconfig
مشاهده فایل 

@@ -325,29 +325,41 @@ config ARCH_B4420
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_B4860
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_BSC9131
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_BSC9132
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_C29X
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_6
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_MPC8536
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_MPC8540
 
@@ -357,20 +369,28 @@ config ARCH_MPC8540
 
 config ARCH_MPC8541
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 
 config ARCH_MPC8544
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_MPC8548
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_MPC8555
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 
 config ARCH_MPC8560
 
 	bool
 
@@ -379,84 +399,118 @@ config ARCH_MPC8560
 
 config ARCH_MPC8568
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 
 config ARCH_MPC8569
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 
 config ARCH_MPC8572
 
 	bool
 
 	select FSL_LAW
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 
 config ARCH_P1010
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P1011
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P1020
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P1021
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P1022
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P1023
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_P1024
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P1025
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P2020
 
 	bool
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_2
 
 	select SYS_PPC_E500_USE_DEBUG_TLB
 
 
 config ARCH_P2041
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_P3041
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_P4080
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_P5020
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_P5040
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_QEMU_E500
 
 	bool
 
@@ -465,41 +519,57 @@ config ARCH_T1023
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_5
 
 
 config ARCH_T1024
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_5
 
 
 config ARCH_T1040
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_5
 
 
 config ARCH_T1042
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_5
 
 
 config ARCH_T2080
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_T2081
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_T4160
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config ARCH_T4240
 
 	bool
 
 	select E500MC
 
 	select FSL_LAW
 
+	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_SEC_COMPAT_4
 
 
 config BOOKE
 
 	bool

+ 0 - 1
arch/powerpc/include/asm/config.h
مشاهده فایل 

@@ -72,7 +72,6 @@
 
  */
 
 #if defined(CONFIG_MPC83xx)
 
 #define CONFIG_SYS_FSL_SEC_BE
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #endif
 
 
 /* Since so many PPC SOCs have a semi-common LBC, define this here */

+ 0 - 30
arch/powerpc/include/asm/config_mpc85xx.h
مشاهده فایل 

@@ -25,7 +25,6 @@
 
 #define CONFIG_SYS_FSL_SEC_MON_BE
 
 
 #if defined(CONFIG_ARCH_MPC8536)
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 
@@ -34,16 +33,13 @@
 
 
 #elif defined(CONFIG_ARCH_MPC8541)
 
 #define CONFIG_SYS_FSL_DDRC_GEN1
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 
 #elif defined(CONFIG_ARCH_MPC8544)
 
 #define CONFIG_SYS_FSL_DDRC_GEN2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 
 #elif defined(CONFIG_ARCH_MPC8548)
 
 #define CONFIG_SYS_FSL_DDRC_GEN2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 
 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 
 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 
@@ -58,14 +54,12 @@
 
 
 #elif defined(CONFIG_ARCH_MPC8555)
 
 #define CONFIG_SYS_FSL_DDRC_GEN1
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 
 #elif defined(CONFIG_ARCH_MPC8560)
 
 #define CONFIG_SYS_FSL_DDRC_GEN1
 
 
 #elif defined(CONFIG_ARCH_MPC8568)
 
 #define CONFIG_SYS_FSL_DDRC_GEN2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define QE_MURAM_SIZE			0x10000UL
 
 #define MAX_QE_RISC			2
 
 #define QE_NUM_OF_SNUM			28
 
@@ -76,7 +70,6 @@
 
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 
 #elif defined(CONFIG_ARCH_MPC8569)
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define QE_MURAM_SIZE			0x20000UL
 
 #define MAX_QE_RISC			4
 
 #define QE_NUM_OF_SNUM			46
 
@@ -89,7 +82,6 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 
 #elif defined(CONFIG_ARCH_MPC8572)
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
 
 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 
@@ -98,7 +90,6 @@
 
 #elif defined(CONFIG_ARCH_P1010)
 
 #define CONFIG_FSL_SDHC_V2_3
 
 #define CONFIG_TSECV2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
@@ -123,7 +114,6 @@
 
 #elif defined(CONFIG_ARCH_P1011)
 
 #define CONFIG_TSECV2
 
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -133,7 +123,6 @@
 
 #elif defined(CONFIG_ARCH_P1020)
 
 #define CONFIG_TSECV2
 
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #define CONFIG_SYS_FSL_ERRATUM_A004508
 
@@ -145,7 +134,6 @@
 
 #elif defined(CONFIG_ARCH_P1021)
 
 #define CONFIG_TSECV2
 
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #define QE_MURAM_SIZE			0x6000UL
 
@@ -157,7 +145,6 @@
 
 
 #elif defined(CONFIG_ARCH_P1022)
 
 #define CONFIG_TSECV2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -167,7 +154,6 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A004477
 
 
 #elif defined(CONFIG_ARCH_P1023)
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 
@@ -185,7 +171,6 @@
 
 #elif defined(CONFIG_ARCH_P1024)
 
 #define CONFIG_TSECV2
 
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
@@ -197,7 +182,6 @@
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #define CONFIG_TSECV2
 
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #define QE_MURAM_SIZE			0x6000UL
 
@@ -207,7 +191,6 @@
 
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 
 #elif defined(CONFIG_ARCH_P2020)
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	2
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
 
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 
@@ -224,7 +207,6 @@
 
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 
@@ -259,7 +241,6 @@
 
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 
@@ -296,7 +277,6 @@
 
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		2
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 
 #define CONFIG_SYS_NUM_FM2_DTSEC	4
 
@@ -345,7 +325,6 @@
 
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 
@@ -378,7 +357,6 @@
 
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		2
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 
@@ -407,7 +385,6 @@
 
 #elif defined(CONFIG_ARCH_BSC9131)
 
 #define CONFIG_FSL_SDHC_V2_3
 
 #define CONFIG_TSECV2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_4
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
@@ -423,7 +400,6 @@
 
 #elif defined(CONFIG_ARCH_BSC9132)
 
 #define CONFIG_FSL_SDHC_V2_3
 
 #define CONFIG_TSECV2
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_6
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
@@ -473,7 +449,6 @@
 
 #define CONFIG_SYS_FSL_SRDS_2
 
 #define CONFIG_SYS_FSL_SRDS_3
 
 #define CONFIG_SYS_FSL_SRDS_4
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		2
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 
 #define CONFIG_SYS_PME_CLK		0
 
@@ -515,7 +490,6 @@
 
 #define CONFIG_SYS_MAPLE
 
 #define CONFIG_SYS_CPRI
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #define CONFIG_SYS_FM1_CLK		0
 
@@ -578,7 +552,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 
 #define CONFIG_SYS_FSL_SRDS_1
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	5
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	5
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 
@@ -624,7 +597,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 
 #define CONFIG_SYS_FSL_NUM_CC_PLL	2
 
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 
 #define CONFIG_SYS_FSL_SRDS_1
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	5
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 
 #define CONFIG_SYS_NUM_FM1_10GEC	1
 
@@ -661,7 +633,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_QMAN_V3
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 
 #define CONFIG_SYS_FSL_SRDS_1
 
@@ -709,7 +680,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 
 #elif defined(CONFIG_ARCH_C29X)
 
 #define CONFIG_FSL_SDHC_V2_3
 
 #define CONFIG_TSECV2_1
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	6
 
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_6

+ 33 - 0
drivers/crypto/fsl/Kconfig
مشاهده فایل 

@@ -4,3 +4,36 @@ config FSL_CAAM
 
 	  Enables the Freescale's Cryptographic Accelerator and Assurance
 
 	  Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
 
 	  Job Ring as interface to communicate with CAAM.
 
+
 
+config SYS_FSL_HAS_SEC
 
+	bool
 
+	help
 
+		Enable Freescale Secure Boot and Trusted Architecture
 
+
 
+config SYS_FSL_SEC_COMPAT_2
 
+	bool
 
+	help
 
+		Secure boot and trust architecture compatible version 2
 
+
 
+config SYS_FSL_SEC_COMPAT_4
 
+	bool
 
+	help
 
+		Secure boot and trust architecture compatible version 4
 
+
 
+config SYS_FSL_SEC_COMPAT_5
 
+	bool
 
+	help
 
+		Secure boot and trust architecture compatible version 5
 
+
 
+config SYS_FSL_SEC_COMPAT_6
 
+	bool
 
+	help
 
+		Secure boot and trust architecture compatible version 6
 
+
 
+config SYS_FSL_SEC_COMPAT
 
+	int "Freescale Secure Boot compatibility"
 
+	depends on SYS_FSL_HAS_SEC
 
+	default 2 if SYS_FSL_SEC_COMPAT_2
 
+	default 4 if SYS_FSL_SEC_COMPAT_4
 
+	default 5 if SYS_FSL_SEC_COMPAT_5
 
+	default 6 if SYS_FSL_SEC_COMPAT_6

+ 0 - 1
include/configs/mx6_common.h
مشاهده فایل 

@@ -94,7 +94,6 @@
 
 /* Secure boot (HAB) support */
 
 #ifdef CONFIG_SECURE_BOOT
 
 #define CONFIG_CSF_SIZE			0x2000
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_FSL_CAAM
 
 #define CONFIG_CMD_DEKBLOB
 
 #define CONFIG_SYS_FSL_SEC_LE

+ 0 - 1
include/configs/mx7_common.h
مشاهده فایل 

@@ -74,7 +74,6 @@
 
 /* Secure boot (HAB) support */
 
 #ifdef CONFIG_SECURE_BOOT
 
 #define CONFIG_CSF_SIZE			0x2000
 
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
 
 #define CONFIG_FSL_CAAM
 
 #define CONFIG_CMD_DEKBLOB
 
 #define CONFIG_SYS_FSL_SEC_LE

+ 0 - 1
scripts/config_whitelist.txt
مشاهده فایل 

@@ -5546,7 +5546,6 @@ CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
 
 CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
 
 CONFIG_SYS_FSL_SEC_ADDR
 
 CONFIG_SYS_FSL_SEC_BE
 
-CONFIG_SYS_FSL_SEC_COMPAT
 
 CONFIG_SYS_FSL_SEC_IDX_OFFSET
 
 CONFIG_SYS_FSL_SEC_LE
 
 CONFIG_SYS_FSL_SEC_MON_BE