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@@ -136,6 +136,7 @@
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR_AXP
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#define CONFIG_SYS_MVEBU_DDR_AXP
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