usb: dwc3: gadget: Set all ctrl fields of Transfer Control Blocks (TRB) to be LST

It turned out that current dwc3 gadget code is preparing multiple TRBs
for a transfer. Unfortunately, when multiple requests are in the same
queue, only for the last one the LST (last) ctrl bit is set.

Due to that dwc3 HW executes all TRBs up till the one marked as last.
Unfortunately, UMS requires call of ->complete callback after any send TRB.
This is the reason for "hangs" in executing UMS.

This code simplifies this situation and set each TRB's ctrl field bit to be
last (LST bit).

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>

drivers/usb/dwc3/gadget.c

@@ -789,7 +789,6 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 	struct dwc3_request	*req, *n;
 	u32			trbs_left;
 	u32			max;
-	unsigned int		last_one = 0;
 
 	BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 
@@ -839,24 +838,14 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 	list_for_each_entry_safe(req, n, &dep->request_list, list) {
 		unsigned	length;
 		dma_addr_t	dma;
-		last_one = false;
 
 		dma = req->request.dma;
 		length = req->request.length;
-		trbs_left--;
-
-		if (!trbs_left)
-			last_one = 1;
-
-		/* Is this the last request? */
-		if (list_is_last(&req->list, &dep->request_list))
-			last_one = 1;
 
 		dwc3_prepare_one_trb(dep, req, dma, length,
-				last_one, false, 0);
+				     true, false, 0);
 
-		if (last_one)
-			break;
+		break;
 	}
 }