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@@ -59,7 +59,6 @@
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#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
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#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
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#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
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#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
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#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
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-#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
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#ifdef CONFIG_ARM64
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#ifdef CONFIG_ARM64
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# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
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# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
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